drm/amd/display: interface to obtain minimum plane size caps

[Why]
Implement an interface to obtain plane size caps

[How]
Add min_width, min_height fields to dc_plane_cap structure.
Set values to 16x16 for discrete ASICs, and 64x64 for others.

Signed-off-by: Igor Kravchenko <Igor.Kravchenko@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e5a1a9eb62175d9a32cb0ea0a4e0c3b1a25f3482..a5faedf6647002a807848f4844b856612208a7e6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -96,6 +96,9 @@ struct dc_plane_cap {
                uint32_t nv12;
                uint32_t fp16;
        } max_downscale_factor;
+       // minimal width/height
+       uint32_t min_width;
+       uint32_t min_height;
 };
 
 // Color management caps (DPP and MPC)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 9597fc79d7faf97e6d09cecc87fb41284638192d..1d5385072a390440b045cccfdd181e4f971021e3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -423,7 +423,9 @@ static const struct dc_plane_cap plane_cap = {
                                .argb8888 = 250,
                                .nv12 = 1,
                                .fp16 = 1
-               }
+               },
+               64,
+               64
 };
 
 static const struct dc_plane_cap underlay_plane_cap = {
@@ -447,7 +449,9 @@ static const struct dc_plane_cap underlay_plane_cap = {
                                .argb8888 = 1,
                                .nv12 = 250,
                                .fp16 = 1
-               }
+               },
+               64,
+               64
 };
 
 #define CTX  ctx

diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 51b3fe50267050ed6de1ae36b5bcd15c687ceeb6..5d83e8174005e6d66de6a699eb1313b354850f50 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -424,7 +424,9 @@ static const struct dc_plane_cap plane_cap = {
                        .argb8888 = 250,
                        .nv12 = 1,
                        .fp16 = 1
-       }
+       },
+       64,
+       64
 };
 
 #define CTX  ctx

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index c8c6225c7e9ea1e541289af14f7f37b69c005c7f..968a89bbcf24283ce45f3d1712509e7d7c95ed93 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1043,7 +1043,9 @@ static const struct dc_plane_cap plane_cap = {
                        .argb8888 = 250,
                        .nv12 = 250,
                        .fp16 = 1
-       }
+       },
+       16,
+       16
 };
 static const struct resource_caps res_cap_nv14 = {
                .num_timing_generator = 5,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 7d82648bec909307f4d70a4e56df7e47150b6fba..88d41a385add8361dcf995701a17c5a59bc8fec7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -857,7 +857,9 @@ static const struct dc_plane_cap plane_cap = {
                        .argb8888 = 250,
                        .nv12 = 250,
                        .fp16 = 250
-       }
+       },
+       64,
+       64
 };
 
 static const struct dc_debug_options debug_defaults_drv = {