intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
+
+ intel_disable_shared_dpll(old_crtc_state);
}
static void hsw_crtc_disable(struct intel_atomic_state *state,
intel_encoders_post_disable(state, crtc);
}
+ intel_disable_shared_dpll(old_crtc_state);
+
intel_dmc_disable_pipe(i915, crtc->pipe);
}
dev_priv->display.funcs.display->crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
- intel_disable_shared_dpll(old_crtc_state);
if (!new_crtc_state->hw.active)
intel_initial_watermarks(state, crtc);