drm/amdgpu/SRIOV: Extend VF reset request wait period

In Virtualization case, when one VF is sending too many
FLR requests, hypervisor would stop responding to this
VF's request for a long period of time. This is called
event guard. During this period of cooling time, guest
driver should wait instead of doing other things. After
this period of time, guest driver would resume reset
process and return to normal.

Currently, guest driver would wait 12 seconds and return fail
if it doesn't get response from host.

Solution: extend this waiting time in guest driver and poll
response periodically. Poll happens every 6 seconds and it will
last for 60 seconds.

v2: change the max repetition times from number to macro.

Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index f5ce9a9f4cf578549bb5e2c22997f93725d02791..7767ccca526bbbe489d9313233c46f1a59801bc3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -187,7 +187,16 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
 
 static int xgpu_ai_request_reset(struct amdgpu_device *adev)
 {
-       return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
+       int ret, i = 0;
+
+       while (i < AI_MAILBOX_POLL_MSG_REP_MAX) {
+               ret = xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
+               if (!ret)
+                       break;
+               i++;
+       }
+
+       return ret;
 }
 
 static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
index 83b453f5d7176616df5f78346422a2c8197e2bfc..50572635d0f80384d82b8092e883943afa04f953 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
@@ -25,8 +25,9 @@
 #define __MXGPU_AI_H__
 
 #define AI_MAILBOX_POLL_ACK_TIMEDOUT   500
-#define AI_MAILBOX_POLL_MSG_TIMEDOUT   12000
+#define AI_MAILBOX_POLL_MSG_TIMEDOUT   6000
 #define AI_MAILBOX_POLL_FLR_TIMEDOUT   5000
+#define AI_MAILBOX_POLL_MSG_REP_MAX    11
 
 enum idh_request {
        IDH_REQ_GPU_INIT_ACCESS = 1,

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
index 666ed99cc14b050bfb56da7ec13f59524855592b..dd5c1e6ce0098716024897b57b2c3d828a32f818 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
@@ -200,7 +200,16 @@ static int xgpu_nv_send_access_requests(struct amdgpu_device *adev,
 
 static int xgpu_nv_request_reset(struct amdgpu_device *adev)
 {
-       return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
+       int ret, i = 0;
+
+       while (i < NV_MAILBOX_POLL_MSG_REP_MAX) {
+               ret = xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
+               if (!ret)
+                       break;
+               i++;
+       }
+
+       return ret;
 }
 
 static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
index 52605e14a1a530457f0a41b3577a29efc6ba56b1..9f58086161749ec946652089146afad4082b08f4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
@@ -27,6 +27,7 @@
 #define NV_MAILBOX_POLL_ACK_TIMEDOUT   500
 #define NV_MAILBOX_POLL_MSG_TIMEDOUT   6000
 #define NV_MAILBOX_POLL_FLR_TIMEDOUT   5000
+#define NV_MAILBOX_POLL_MSG_REP_MAX    11
 
 enum idh_request {
        IDH_REQ_GPU_INIT_ACCESS = 1,