drm/i915: update the QGV point frequency calculations

From MTL onwwards, pcode locks the QGV point based on peak BW of
the intended QGV point passed by the driver. So the peak BW
calculation must match the value expected by the pcode. Update
the calculations as per the Bspec.

v2: use DIV_ROUND_* macro for the calculations (Ville)

v3: Use only DIV_ROUN_CLOSEST and remove divisor / 2 again

Bspec: 64636

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606093509.221709-3-vinod.govindapillai@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index ab405c48ca3a9c66dc5b62998c1f93bbaf16c791..61b3babf2d83746da48bcbcb5c924a4ec40013ec 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -182,7 +182,7 @@ static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
        val2 = intel_uncore_read(&dev_priv->uncore,
                                 MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
        dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
-       sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
+       sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000);
        sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
        sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);