RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()

On ACPI based systems, the information about the hart
like ISA is provided by the RISC-V Hart Capabilities Table (RHCT).
Enable filling up hwcap structure based on the information in RHCT.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230515054928.2079268-15-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index c607db2c842c902ee4ffb9b7733fb9108a21fb27..6ba8e20c5346f9f561685e9c3e832e4c5a4c74d2 100644 (file)
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -6,6 +6,7 @@
  * Copyright (C) 2017 SiFive
  */
 
+#include <linux/acpi.h>
 #include <linux/bitmap.h>
 #include <linux/ctype.h>
 #include <linux/log2.h>
@@ -13,6 +14,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <asm/acpi.h>
 #include <asm/alternative.h>
 #include <asm/cacheflush.h>
 #include <asm/cpufeature.h>
@@ -100,6 +102,8 @@ void __init riscv_fill_hwcap(void)
        char print_str[NUM_ALPHA_EXTS + 1];
        int i, j, rc;
        unsigned long isa2hwcap[26] = {0};
+       struct acpi_table_header *rhct;
+       acpi_status status;
        unsigned int cpu;
 
        isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
@@ -113,22 +117,36 @@ void __init riscv_fill_hwcap(void)
 
        bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
 
+       if (!acpi_disabled) {
+               status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
+               if (ACPI_FAILURE(status))
+                       return;
+       }
+
        for_each_possible_cpu(cpu) {
                unsigned long this_hwcap = 0;
                DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
                const char *temp;
 
-               node = of_cpu_device_node_get(cpu);
-               if (!node) {
-                       pr_warn("Unable to find cpu node\n");
-                       continue;
-               }
+               if (acpi_disabled) {
+                       node = of_cpu_device_node_get(cpu);
+                       if (!node) {
+                               pr_warn("Unable to find cpu node\n");
+                               continue;
+                       }
 
-               rc = of_property_read_string(node, "riscv,isa", &isa);
-               of_node_put(node);
-               if (rc) {
-                       pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
-                       continue;
+                       rc = of_property_read_string(node, "riscv,isa", &isa);
+                       of_node_put(node);
+                       if (rc) {
+                               pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
+                               continue;
+                       }
+               } else {
+                       rc = acpi_get_riscv_isa(rhct, cpu, &isa);
+                       if (rc < 0) {
+                               pr_warn("Unable to get ISA for the hart - %d\n", cpu);
+                               continue;
+                       }
                }
 
                temp = isa;
@@ -265,6 +283,9 @@ void __init riscv_fill_hwcap(void)
                        bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
        }
 
+       if (!acpi_disabled && rhct)
+               acpi_put_table((struct acpi_table_header *)rhct);
+
        /* We don't support systems with F but without D, so mask those out
         * here. */
        if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {