clk: sunxi-ng: h6-r: Add RTC gate clock

The H6 and H616 feature an (undocumented) bus clock gate for accessing
the RTC registers. This seems to be enabled at reset (or by the BootROM),
so we got away without it so far, but exists regardless.
Since the new RTC clock binding for the H616 requires this "bus" clock
to be specified in the DT, add this to R_CCU clock driver and expose it
on the DT side with a new number.
We do this for both the H6 and H616, but mark it as IGNORE_UNUSED, as we
cannot reference it in any H6 DTs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220428230933.15262-2-andre.przywara@arm.com

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 712e103382d8057a2ae080f063ae91d59527f7ed..29a8c710ae068133aa70bd4ae3bcce63b23c0368 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -98,6 +98,8 @@ static SUNXI_CCU_GATE(r_apb1_ir_clk,  "r-apb1-ir",    "r-apb1",
                      0x1cc, BIT(0), 0);
 static SUNXI_CCU_GATE(r_apb1_w1_clk,   "r-apb1-w1",    "r-apb1",
                      0x1ec, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb1_rtc_clk,  "r-apb1-rtc",   "r-apb1",
+                     0x20c, BIT(0), CLK_IGNORE_UNUSED);
 
 /* Information of IR(RX) mod clock is gathered from BSP source code */
 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
@@ -147,6 +149,7 @@ static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
        &r_apb2_i2c_clk.common,
        &r_apb2_rsb_clk.common,
        &r_apb1_ir_clk.common,
+       &r_apb1_rtc_clk.common,
        &ir_clk.common,
 };
 
@@ -164,6 +167,7 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
                [CLK_R_APB2_RSB]        = &r_apb2_rsb_clk.common.hw,
                [CLK_R_APB1_IR]         = &r_apb1_ir_clk.common.hw,
                [CLK_R_APB1_W1]         = &r_apb1_w1_clk.common.hw,
+               [CLK_R_APB1_RTC]        = &r_apb1_rtc_clk.common.hw,
                [CLK_IR]                = &ir_clk.common.hw,
                [CLK_W1]                = &w1_clk.common.hw,
        },
@@ -179,6 +183,7 @@ static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
                [CLK_R_APB2_I2C]        = &r_apb2_i2c_clk.common.hw,
                [CLK_R_APB2_RSB]        = &r_apb2_rsb_clk.common.hw,
                [CLK_R_APB1_IR]         = &r_apb1_ir_clk.common.hw,
+               [CLK_R_APB1_RTC]        = &r_apb1_rtc_clk.common.hw,
                [CLK_IR]                = &ir_clk.common.hw,
        },
        .num    = CLK_NUMBER,

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
index 7e290b840803564b62e5743fb314fe38179fe4cd..10e9b66afc6a9ae0bb50a9f90198fc933dbdc7d4 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
@@ -14,6 +14,6 @@
 
 #define CLK_R_APB2     3
 
-#define CLK_NUMBER     (CLK_R_APB2_RSB + 1)
+#define CLK_NUMBER     (CLK_R_APB1_RTC + 1)
 
 #endif /* _CCU_SUN50I_H6_R_H */

diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
index 890368d252c455316bef24baf921ccd01d33594e..a96087abc86fbec9b13bd01962b67151b227dec0 100644 (file)
--- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h
+++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
@@ -22,5 +22,6 @@
 #define CLK_W1                 12
 
 #define CLK_R_APB2_RSB         13
+#define CLK_R_APB1_RTC         14
 
 #endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */