x86/sev: Prevent GUEST_TSC_FREQ MSR interception for Secure TSC enabled guests

The hypervisor should not be intercepting GUEST_TSC_FREQ MSR(0xcOO10134)
when Secure TSC is enabled. A #VC exception will be generated otherwise. If
this should occur and Secure TSC is enabled, terminate guest execution.

Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Link: https://lore.kernel.org/r/20250106124633.1418972-8-nikunj@amd.com

diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
index cd5b9b7237555fd0e28631394d801b6c7de07ca4..106bdeda58c51607ba3315810e273f3bfaa23cef 100644 (file)
--- a/arch/x86/coco/sev/core.c
+++ b/arch/x86/coco/sev/core.c
@@ -1436,12 +1436,19 @@ static enum es_result __vc_handle_msr_caa(struct pt_regs *regs, bool write)
 /*
  * TSC related accesses should not exit to the hypervisor when a guest is
  * executing with Secure TSC enabled, so special handling is required for
- * accesses of MSR_IA32_TSC.
+ * accesses of MSR_IA32_TSC and MSR_AMD64_GUEST_TSC_FREQ.
  */
 static enum es_result __vc_handle_secure_tsc_msrs(struct pt_regs *regs, bool write)
 {
        u64 tsc;
 
+       /*
+        * GUEST_TSC_FREQ should not be intercepted when Secure TSC is enabled.
+        * Terminate the SNP guest when the interception is enabled.
+        */
+       if (regs->cx == MSR_AMD64_GUEST_TSC_FREQ)
+               return ES_VMM_ERROR;
+
        /*
         * Writes: Writing to MSR_IA32_TSC can cause subsequent reads of the TSC
         *         to return undefined values, so ignore all writes.
@@ -1474,6 +1481,7 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
        case MSR_SVSM_CAA:
                return __vc_handle_msr_caa(regs, write);
        case MSR_IA32_TSC:
+       case MSR_AMD64_GUEST_TSC_FREQ:
                if (sev_status & MSR_AMD64_SNP_SECURE_TSC)
                        return __vc_handle_secure_tsc_msrs(regs, write);
                else

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3f3e2bc99162c55ad39f455f3580536097566bb2..9a71880eec0700b11989ffaec2eb5941d35042f3 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -608,6 +608,7 @@
 #define MSR_AMD_PERF_CTL               0xc0010062
 #define MSR_AMD_PERF_STATUS            0xc0010063
 #define MSR_AMD_PSTATE_DEF_BASE                0xc0010064
+#define MSR_AMD64_GUEST_TSC_FREQ       0xc0010134
 #define MSR_AMD64_OSVW_ID_LENGTH       0xc0010140
 #define MSR_AMD64_OSVW_STATUS          0xc0010141
 #define MSR_AMD_PPIN_CTL               0xc00102f0