drm/amdgpu/vcn2.0: convert internal functions to use vcn_inst

Pass the vcn instance structure to these functions rather
than adev and the instance number.

TODO: clean up the function internals to use the vinst state
directly rather than accessing it indirectly via adev->vcn.inst[].

v2: index instances directly on vcn1.0 and 2.0 to make
it clear that they only support a single instance (Lijo)

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 5f537d2a5618cd95f127d03b1d9d18dc9a7f4e24..43672ba236e3caf7dc5ff02ec9177a3c691536da 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -370,8 +370,9 @@ static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block)
  *
  * Let the VCN memory controller know it's offsets
  */
-static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
+static void vcn_v2_0_mc_resume(struct amdgpu_vcn_inst *vinst)
 {
+       struct amdgpu_device *adev = vinst->adev;
        uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
        uint32_t offset;
 
@@ -426,8 +427,10 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
        WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 }
 
-static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
+static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                       bool indirect)
 {
+       struct amdgpu_device *adev = vinst->adev;
        uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
        uint32_t offset;
 
@@ -525,12 +528,13 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
 /**
  * vcn_v2_0_disable_clock_gating - disable VCN clock gating
  *
- * @adev: amdgpu_device pointer
+ * @vinst: VCN instance
  *
  * Disable clock gating for VCN block
  */
-static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
+static void vcn_v2_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)
 {
+       struct amdgpu_device *adev = vinst->adev;
        uint32_t data;
 
        if (amdgpu_sriov_vf(adev))
@@ -634,9 +638,10 @@ static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
        WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 }
 
-static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
+static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,
                uint8_t sram_sel, uint8_t indirect)
 {
+       struct amdgpu_device *adev = vinst->adev;
        uint32_t reg_data = 0;
 
        /* enable sw clock gating control */
@@ -685,12 +690,13 @@ static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
 /**
  * vcn_v2_0_enable_clock_gating - enable VCN clock gating
  *
- * @adev: amdgpu_device pointer
+ * @vinst: VCN instance
  *
  * Enable clock gating for VCN block
  */
-static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
+static void vcn_v2_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)
 {
+       struct amdgpu_device *adev = vinst->adev;
        uint32_t data = 0;
 
        if (amdgpu_sriov_vf(adev))
@@ -743,8 +749,9 @@ static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
        WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 }
 
-static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
+static void vcn_v2_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)
 {
+       struct amdgpu_device *adev = vinst->adev;
        uint32_t data = 0;
 
        if (amdgpu_sriov_vf(adev))
@@ -792,8 +799,9 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
        WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 }
 
-static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
+static void vcn_v2_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)
 {
+       struct amdgpu_device *adev = vinst->adev;
        uint32_t data = 0;
 
        if (amdgpu_sriov_vf(adev))
@@ -834,13 +842,14 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
        }
 }
 
-static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
+static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
 {
+       struct amdgpu_device *adev = vinst->adev;
        volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
        struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
        uint32_t rb_bufsz, tmp;
 
-       vcn_v2_0_enable_static_power_gating(adev);
+       vcn_v2_0_enable_static_power_gating(vinst);
 
        /* enable dynamic power gating mode */
        tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
@@ -852,7 +861,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
                adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr;
 
        /* enable clock gating */
-       vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
+       vcn_v2_0_clock_gating_dpg_mode(vinst, 0, indirect);
 
        /* enable VCPU clock */
        tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
@@ -901,7 +910,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
                 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
                 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 
-       vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
+       vcn_v2_0_mc_resume_dpg_mode(vinst, indirect);
 
        WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
                UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
@@ -969,8 +978,9 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
        return 0;
 }
 
-static int vcn_v2_0_start(struct amdgpu_device *adev)
+static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst)
 {
+       struct amdgpu_device *adev = vinst->adev;
        volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
        struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
        uint32_t rb_bufsz, tmp;
@@ -981,16 +991,16 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
                amdgpu_dpm_enable_vcn(adev, true, 0);
 
        if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
-               return vcn_v2_0_start_dpg_mode(adev, adev->vcn.inst->indirect_sram);
+               return vcn_v2_0_start_dpg_mode(vinst, adev->vcn.inst->indirect_sram);
 
-       vcn_v2_0_disable_static_power_gating(adev);
+       vcn_v2_0_disable_static_power_gating(vinst);
 
        /* set uvd status busy */
        tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
        WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 
        /*SW clock gating */
-       vcn_v2_0_disable_clock_gating(adev);
+       vcn_v2_0_disable_clock_gating(vinst);
 
        /* enable VCPU clock */
        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
@@ -1034,7 +1044,7 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
                (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
                (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 
-       vcn_v2_0_mc_resume(adev);
+       vcn_v2_0_mc_resume(vinst);
 
        /* release VCPU reset to boot */
        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
@@ -1142,8 +1152,9 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
        return 0;
 }
 
-static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
+static int vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
 {
+       struct amdgpu_device *adev = vinst->adev;
        struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
        uint32_t tmp;
 
@@ -1172,13 +1183,14 @@ static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
        return 0;
 }
 
-static int vcn_v2_0_stop(struct amdgpu_device *adev)
+static int vcn_v2_0_stop(struct amdgpu_vcn_inst *vinst)
 {
+       struct amdgpu_device *adev = vinst->adev;
        uint32_t tmp;
        int r;
 
        if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
-               r = vcn_v2_0_stop_dpg_mode(adev);
+               r = vcn_v2_0_stop_dpg_mode(vinst);
                if (r)
                        return r;
                goto power_off;
@@ -1230,8 +1242,8 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
        /* clear status */
        WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
 
-       vcn_v2_0_enable_clock_gating(adev);
-       vcn_v2_0_enable_static_power_gating(adev);
+       vcn_v2_0_enable_clock_gating(vinst);
+       vcn_v2_0_enable_static_power_gating(vinst);
 
 power_off:
        if (adev->pm.dpm_enabled)
@@ -1348,10 +1360,10 @@ static int vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
                /* wait for STATUS to clear */
                if (!vcn_v2_0_is_idle(ip_block))
                        return -EBUSY;
-               vcn_v2_0_enable_clock_gating(adev);
+               vcn_v2_0_enable_clock_gating(&adev->vcn.inst[0]);
        } else {
                /* disable HW gating and enable Sw gating */
-               vcn_v2_0_disable_clock_gating(adev);
+               vcn_v2_0_disable_clock_gating(&adev->vcn.inst[0]);
        }
        return 0;
 }
@@ -1818,9 +1830,9 @@ static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                return 0;
 
        if (state == AMD_PG_STATE_GATE)
-               ret = vcn_v2_0_stop(adev);
+               ret = vcn_v2_0_stop(adev->vcn.inst);
        else
-               ret = vcn_v2_0_start(adev);
+               ret = vcn_v2_0_start(adev->vcn.inst);
 
        if (!ret)
                adev->vcn.inst[0].cur_state = state;