struct amdgpu_display_manager *dm = &drm_to_adev(drm_dev)->dm;
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
bool was_activated;
+ uint8_t phy_id = stream->link->link_enc_hw_inst;
spin_lock_irq(&drm_dev->event_lock);
was_activated = acrtc->dm_irq_params.window_param.activated;
/* stop ROI update on this crtc */
flush_work(&dm->secure_display_ctxs[crtc->index].notify_ta_work);
flush_work(&dm->secure_display_ctxs[crtc->index].forward_roi_work);
- dc_stream_forward_crc_window(stream, NULL, true);
+ dc_stream_forward_crc_window(stream, NULL, phy_id, true);
}
}
stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream;
mutex_lock(&dm->dc_lock);
- dc_stream_forward_crc_window(stream, &secure_display_ctx->rect, false);
+ dc_stream_forward_crc_window(stream, &secure_display_ctx->rect,
+ stream->link->link_enc_hw_inst, false);
mutex_unlock(&dm->dc_lock);
}
bool
dc_stream_forward_crc_window(struct dc_stream_state *stream,
- struct rect *rect, bool is_stop)
+ struct rect *rect, uint8_t phy_id, bool is_stop)
{
struct dmcu *dmcu;
struct dc_dmub_srv *dmub_srv;
if (i == MAX_PIPES)
return false;
- mux_mapping.phy_output_num = stream->link->link_enc_hw_inst;
+ mux_mapping.phy_output_num = phy_id;
mux_mapping.otg_output_num = pipe->stream_res.tg->inst;
dmcu = dc->res_pool->dmcu;