drm/amdgpu/gfx12: recalculate available compute rings to use

Recalculate the number of compute rings to use based on
the gfx hardware configuration. As needed reserve half of
compute rings for mes, kgd can't use up all compute rings.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index f3f8601d6e1841c492f1ff680ccd01ba893f28e8..06244d97c283164c200a6c2158447d5a29cc8147 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -1103,6 +1103,7 @@ static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
 static int gfx_v12_0_sw_init(void *handle)
 {
        int i, j, k, r, ring_id = 0;
+       unsigned num_compute_rings;
        int xcc_id = 0;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
@@ -1126,6 +1127,12 @@ static int gfx_v12_0_sw_init(void *handle)
                break;
        }
 
+       /* recalculate compute rings to use based on hardware configuration */
+       num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
+                            adev->gfx.mec.num_queue_per_pipe) / 2;
+       adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
+                                         num_compute_rings);
+
        /* EOP Event */
        r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
                              GFX_11_0_0__SRCID__CP_EOP_INTERRUPT,