x86/MCE/AMD, EDAC/mce_amd: Remove struct smca_hwid.xec_bitmap

The Extended Error Code Bitmap (xec_bitmap) for a Scalable MCA bank type
was intended to be used by the kernel to filter out invalid error codes
on a system. However, this is unnecessary after a few product releases
because the hardware will only report valid error codes. Thus, there's
no need for it with future systems.

Remove the xec_bitmap field and all references to it.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200720145353.43924-1-Yazen.Ghannam@amd.com

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index cf503824529ced346b7f297fe0cf1a9f337ea39c..6adced6e7dd3573a5a705522e80880020dfed1ec 100644 (file)
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -328,7 +328,6 @@ enum smca_bank_types {
 struct smca_hwid {
        unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
        u32 hwid_mcatype;       /* (hwid,mcatype) tuple */
-       u32 xec_bitmap;         /* Bitmap of valid ExtErrorCodes; current max is 21. */
        u8 count;               /* Number of instances. */
 };
 

diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 99be063fcb1bb1c6fc335581006b49be4df2fa98..0c6b02dd744c1424c3235035aab439d2f1d0d1b8 100644 (file)
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -132,49 +132,49 @@ static enum smca_bank_types smca_get_bank_type(unsigned int bank)
 }
 
 static struct smca_hwid smca_hwid_mcatypes[] = {
-       /* { bank_type, hwid_mcatype, xec_bitmap } */
+       /* { bank_type, hwid_mcatype } */
 
        /* Reserved type */
-       { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 },
+       { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0)        },
 
        /* ZN Core (HWID=0xB0) MCA types */
-       { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0), 0x1FFFFF },
-       { SMCA_LS_V2,    HWID_MCATYPE(0xB0, 0x10), 0xFFFFFF },
-       { SMCA_IF,       HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
-       { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
-       { SMCA_DE,       HWID_MCATYPE(0xB0, 0x3), 0x1FF },
+       { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0)        },
+       { SMCA_LS_V2,    HWID_MCATYPE(0xB0, 0x10)       },
+       { SMCA_IF,       HWID_MCATYPE(0xB0, 0x1)        },
+       { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2)        },
+       { SMCA_DE,       HWID_MCATYPE(0xB0, 0x3)        },
        /* HWID 0xB0 MCATYPE 0x4 is Reserved */
-       { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5), 0xFFF },
-       { SMCA_FP,       HWID_MCATYPE(0xB0, 0x6), 0x7F },
-       { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
+       { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5)        },
+       { SMCA_FP,       HWID_MCATYPE(0xB0, 0x6)        },
+       { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7)        },
 
        /* Data Fabric MCA types */
-       { SMCA_CS,       HWID_MCATYPE(0x2E, 0x0), 0x1FF },
-       { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1), 0x1F },
-       { SMCA_CS_V2,    HWID_MCATYPE(0x2E, 0x2), 0x3FFF },
+       { SMCA_CS,       HWID_MCATYPE(0x2E, 0x0)        },
+       { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1)        },
+       { SMCA_CS_V2,    HWID_MCATYPE(0x2E, 0x2)        },
 
        /* Unified Memory Controller MCA type */
-       { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0), 0xFF },
+       { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0)        },
 
        /* Parameter Block MCA type */
-       { SMCA_PB,       HWID_MCATYPE(0x05, 0x0), 0x1 },
+       { SMCA_PB,       HWID_MCATYPE(0x05, 0x0)        },
 
        /* Platform Security Processor MCA type */
-       { SMCA_PSP,      HWID_MCATYPE(0xFF, 0x0), 0x1 },
-       { SMCA_PSP_V2,   HWID_MCATYPE(0xFF, 0x1), 0x3FFFF },
+       { SMCA_PSP,      HWID_MCATYPE(0xFF, 0x0)        },
+       { SMCA_PSP_V2,   HWID_MCATYPE(0xFF, 0x1)        },
 
        /* System Management Unit MCA type */
-       { SMCA_SMU,      HWID_MCATYPE(0x01, 0x0), 0x1 },
-       { SMCA_SMU_V2,   HWID_MCATYPE(0x01, 0x1), 0x7FF },
+       { SMCA_SMU,      HWID_MCATYPE(0x01, 0x0)        },
+       { SMCA_SMU_V2,   HWID_MCATYPE(0x01, 0x1)        },
 
        /* Microprocessor 5 Unit MCA type */
-       { SMCA_MP5,      HWID_MCATYPE(0x01, 0x2), 0x3FF },
+       { SMCA_MP5,      HWID_MCATYPE(0x01, 0x2)        },
 
        /* Northbridge IO Unit MCA type */
-       { SMCA_NBIO,     HWID_MCATYPE(0x18, 0x0), 0x1F },
+       { SMCA_NBIO,     HWID_MCATYPE(0x18, 0x0)        },
 
        /* PCI Express Unit MCA type */
-       { SMCA_PCIE,     HWID_MCATYPE(0x46, 0x0), 0x1F },
+       { SMCA_PCIE,     HWID_MCATYPE(0x46, 0x0)        },
 };
 
 struct smca_bank smca_banks[MAX_NR_BANKS];

diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index 325aedf46ff2b864328a391ab9d8f300b7ed890b..d4168c46739c7b9dbdf73a07f3e41d3f49d8e074 100644 (file)
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -990,10 +990,8 @@ static void decode_smca_error(struct mce *m)
        pr_emerg(HW_ERR "%s Ext. Error Code: %d", ip_name, xec);
 
        /* Only print the decode of valid error codes */
-       if (xec < smca_mce_descs[bank_type].num_descs &&
-                       (hwid->xec_bitmap & BIT_ULL(xec))) {
+       if (xec < smca_mce_descs[bank_type].num_descs)
                pr_cont(", %s.\n", smca_mce_descs[bank_type].descs[xec]);
-       }
 
        if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc)
                decode_dram_ecc(cpu_to_node(m->extcpu), m);