arm64: dts: qcom: qdu1000: Add secure qfprom node

Add secure qfprom node and also add properties for multi channel
DDR. This is required for LLCC driver to pick the correct LLCC
configuration.

Fixes: 6209038f131f ("arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller")
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>
Link: https://lore.kernel.org/r/20240618092711.15037-1-quic_kbajaj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 7a77f7a55498fe115e030fc905660652e72e22ae..27f9fc87079c5a32b336ba94f6aee62b24876b3c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -1584,6 +1584,21 @@
                        reg-names = "llcc0_base",
                                    "llcc_broadcast_base";
                        interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+
+                       nvmem-cells = <&multi_chan_ddr>;
+                       nvmem-cell-names = "multi-chan-ddr";
+               };
+
+               sec_qfprom: efuse@221c8000 {
+                       compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom";
+                       reg = <0 0x221c8000 0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       multi_chan_ddr: multi-chan-ddr@12b {
+                               reg = <0x12b 0x1>;
+                               bits = <0 2>;
+                       };
                };
        };