arm64: tools: Resync sysreg.h

Perform a bulk resync of tools/arch/arm64/include/asm/sysreg.h.

Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h
index b6c5ece4fdee74b75b71aedf0201e0c9fea35e44..690b6ebd118f4f5dbbe582ee54751ee6534b1d00 100644 (file)
--- a/tools/arch/arm64/include/asm/sysreg.h
+++ b/tools/arch/arm64/include/asm/sysreg.h
@@ -117,6 +117,7 @@
 
 #define SB_BARRIER_INSN                        __SYS_BARRIER_INSN(0, 7, 31)
 
+/* Data cache zero operations */
 #define SYS_DC_ISW                     sys_insn(1, 0, 7, 6, 2)
 #define SYS_DC_IGSW                    sys_insn(1, 0, 7, 6, 4)
 #define SYS_DC_IGDSW                   sys_insn(1, 0, 7, 6, 6)
@@ -153,11 +154,13 @@
 #define SYS_DC_CIGVAC                  sys_insn(1, 3, 7, 14, 3)
 #define SYS_DC_CIGDVAC                 sys_insn(1, 3, 7, 14, 5)
 
-/* Data cache zero operations */
 #define SYS_DC_ZVA                     sys_insn(1, 3, 7, 4, 1)
 #define SYS_DC_GVA                     sys_insn(1, 3, 7, 4, 3)
 #define SYS_DC_GZVA                    sys_insn(1, 3, 7, 4, 4)
 
+#define SYS_DC_CIVAPS                  sys_insn(1, 0, 7, 15, 1)
+#define SYS_DC_CIGDVAPS                        sys_insn(1, 0, 7, 15, 5)
+
 /*
  * Automatically generated definitions for system registers, the
  * manual encodings below are in the process of being converted to
@@ -475,6 +478,7 @@
 #define SYS_CNTFRQ_EL0                 sys_reg(3, 3, 14, 0, 0)
 
 #define SYS_CNTPCT_EL0                 sys_reg(3, 3, 14, 0, 1)
+#define SYS_CNTVCT_EL0                 sys_reg(3, 3, 14, 0, 2)
 #define SYS_CNTPCTSS_EL0               sys_reg(3, 3, 14, 0, 5)
 #define SYS_CNTVCTSS_EL0               sys_reg(3, 3, 14, 0, 6)
 
@@ -482,23 +486,36 @@
 #define SYS_CNTP_CTL_EL0               sys_reg(3, 3, 14, 2, 1)
 #define SYS_CNTP_CVAL_EL0              sys_reg(3, 3, 14, 2, 2)
 
+#define SYS_CNTV_TVAL_EL0              sys_reg(3, 3, 14, 3, 0)
 #define SYS_CNTV_CTL_EL0               sys_reg(3, 3, 14, 3, 1)
 #define SYS_CNTV_CVAL_EL0              sys_reg(3, 3, 14, 3, 2)
 
 #define SYS_AARCH32_CNTP_TVAL          sys_reg(0, 0, 14, 2, 0)
 #define SYS_AARCH32_CNTP_CTL           sys_reg(0, 0, 14, 2, 1)
 #define SYS_AARCH32_CNTPCT             sys_reg(0, 0, 0, 14, 0)
+#define SYS_AARCH32_CNTVCT             sys_reg(0, 1, 0, 14, 0)
 #define SYS_AARCH32_CNTP_CVAL          sys_reg(0, 2, 0, 14, 0)
 #define SYS_AARCH32_CNTPCTSS           sys_reg(0, 8, 0, 14, 0)
+#define SYS_AARCH32_CNTVCTSS           sys_reg(0, 9, 0, 14, 0)
 
 #define __PMEV_op2(n)                  ((n) & 0x7)
 #define __CNTR_CRm(n)                  (0x8 | (((n) >> 3) & 0x3))
+#define SYS_PMEVCNTSVRn_EL1(n)         sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n))
 #define SYS_PMEVCNTRn_EL0(n)           sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
 #define __TYPER_CRm(n)                 (0xc | (((n) >> 3) & 0x3))
 #define SYS_PMEVTYPERn_EL0(n)          sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
 
 #define SYS_PMCCFILTR_EL0              sys_reg(3, 3, 14, 15, 7)
 
+#define        SYS_SPMCGCRn_EL1(n)             sys_reg(2, 0, 9, 13, ((n) & 1))
+
+#define __SPMEV_op2(n)                 ((n) & 0x7)
+#define __SPMEV_crm(p, n)              ((((p) & 7) << 1) | (((n) >> 3) & 1))
+#define SYS_SPMEVCNTRn_EL0(n)          sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n))
+#define        SYS_SPMEVFILT2Rn_EL0(n)         sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n))
+#define        SYS_SPMEVFILTRn_EL0(n)          sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n))
+#define        SYS_SPMEVTYPERn_EL0(n)          sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n))
+
 #define SYS_VPIDR_EL2                  sys_reg(3, 4, 0, 0, 0)
 #define SYS_VMPIDR_EL2                 sys_reg(3, 4, 0, 0, 5)
 
@@ -518,7 +535,6 @@
 #define SYS_VTCR_EL2                   sys_reg(3, 4, 2, 1, 2)
 
 #define SYS_VNCR_EL2                   sys_reg(3, 4, 2, 2, 0)
-#define SYS_HAFGRTR_EL2                        sys_reg(3, 4, 3, 1, 6)
 #define SYS_SPSR_EL2                   sys_reg(3, 4, 4, 0, 0)
 #define SYS_ELR_EL2                    sys_reg(3, 4, 4, 0, 1)
 #define SYS_SP_EL1                     sys_reg(3, 4, 4, 1, 0)
@@ -604,28 +620,18 @@
 
 /* VHE encodings for architectural EL0/1 system registers */
 #define SYS_BRBCR_EL12                 sys_reg(2, 5, 9, 0, 0)
-#define SYS_SCTLR_EL12                 sys_reg(3, 5, 1, 0, 0)
-#define SYS_CPACR_EL12                 sys_reg(3, 5, 1, 0, 2)
-#define SYS_SCTLR2_EL12                        sys_reg(3, 5, 1, 0, 3)
-#define SYS_ZCR_EL12                   sys_reg(3, 5, 1, 2, 0)
-#define SYS_TRFCR_EL12                 sys_reg(3, 5, 1, 2, 1)
-#define SYS_SMCR_EL12                  sys_reg(3, 5, 1, 2, 6)
 #define SYS_TTBR0_EL12                 sys_reg(3, 5, 2, 0, 0)
 #define SYS_TTBR1_EL12                 sys_reg(3, 5, 2, 0, 1)
-#define SYS_TCR_EL12                   sys_reg(3, 5, 2, 0, 2)
-#define SYS_TCR2_EL12                  sys_reg(3, 5, 2, 0, 3)
 #define SYS_SPSR_EL12                  sys_reg(3, 5, 4, 0, 0)
 #define SYS_ELR_EL12                   sys_reg(3, 5, 4, 0, 1)
 #define SYS_AFSR0_EL12                 sys_reg(3, 5, 5, 1, 0)
 #define SYS_AFSR1_EL12                 sys_reg(3, 5, 5, 1, 1)
 #define SYS_ESR_EL12                   sys_reg(3, 5, 5, 2, 0)
 #define SYS_TFSR_EL12                  sys_reg(3, 5, 5, 6, 0)
-#define SYS_FAR_EL12                   sys_reg(3, 5, 6, 0, 0)
 #define SYS_PMSCR_EL12                 sys_reg(3, 5, 9, 9, 0)
 #define SYS_MAIR_EL12                  sys_reg(3, 5, 10, 2, 0)
 #define SYS_AMAIR_EL12                 sys_reg(3, 5, 10, 3, 0)
 #define SYS_VBAR_EL12                  sys_reg(3, 5, 12, 0, 0)
-#define SYS_CONTEXTIDR_EL12            sys_reg(3, 5, 13, 0, 1)
 #define SYS_SCXTNUM_EL12               sys_reg(3, 5, 13, 0, 7)
 #define SYS_CNTKCTL_EL12               sys_reg(3, 5, 14, 1, 0)
 #define SYS_CNTP_TVAL_EL02             sys_reg(3, 5, 14, 2, 0)
@@ -1028,8 +1034,11 @@
 #define PIE_RX         UL(0xa)
 #define PIE_RW         UL(0xc)
 #define PIE_RWX                UL(0xe)
+#define PIE_MASK       UL(0xf)
 
-#define PIRx_ELx_PERM(idx, perm)       ((perm) << ((idx) * 4))
+#define PIRx_ELx_BITS_PER_IDX          4
+#define PIRx_ELx_PERM_SHIFT(idx)       ((idx) * PIRx_ELx_BITS_PER_IDX)
+#define PIRx_ELx_PERM_PREP(idx, perm)  (((perm) & PIE_MASK) << PIRx_ELx_PERM_SHIFT(idx))
 
 /*
  * Permission Overlay Extension (POE) permission encodings.
@@ -1040,12 +1049,34 @@
 #define POE_RX         UL(0x3)
 #define POE_W          UL(0x4)
 #define POE_RW         UL(0x5)
-#define POE_XW         UL(0x6)
-#define POE_RXW                UL(0x7)
+#define POE_WX         UL(0x6)
+#define POE_RWX                UL(0x7)
 #define POE_MASK       UL(0xf)
 
-/* Initial value for Permission Overlay Extension for EL0 */
-#define POR_EL0_INIT   POE_RXW
+#define POR_ELx_BITS_PER_IDX           4
+#define POR_ELx_PERM_SHIFT(idx)                ((idx) * POR_ELx_BITS_PER_IDX)
+#define POR_ELx_PERM_GET(idx, reg)     (((reg) >> POR_ELx_PERM_SHIFT(idx)) & POE_MASK)
+#define POR_ELx_PERM_PREP(idx, perm)   (((perm) & POE_MASK) << POR_ELx_PERM_SHIFT(idx))
+
+/*
+ * Definitions for Guarded Control Stack
+ */
+
+#define GCS_CAP_ADDR_MASK              GENMASK(63, 12)
+#define GCS_CAP_ADDR_SHIFT             12
+#define GCS_CAP_ADDR_WIDTH             52
+#define GCS_CAP_ADDR(x)                        FIELD_GET(GCS_CAP_ADDR_MASK, x)
+
+#define GCS_CAP_TOKEN_MASK             GENMASK(11, 0)
+#define GCS_CAP_TOKEN_SHIFT            0
+#define GCS_CAP_TOKEN_WIDTH            12
+#define GCS_CAP_TOKEN(x)               FIELD_GET(GCS_CAP_TOKEN_MASK, x)
+
+#define GCS_CAP_VALID_TOKEN            0x1
+#define GCS_CAP_IN_PROGRESS_TOKEN      0x5
+
+#define GCS_CAP(x)     ((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \
+                                              GCS_CAP_VALID_TOKEN)
 
 #define ARM64_FEATURE_FIELD_BITS       4