clk: renesas: rzv2h: Rename PLL field macros for consistency

Rename PLL field extraction macros to include the associated register name
(`CPG_PLL_CLK1` or `CPG_PLL_CLK2`) to maintain consistency with other PLL
register macros. Update all corresponding macro references accordingly.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index fd9d401d184fe53b227642c5e0e24f0121151c95..b8bed0c1d9186e556592ec1eff7d90f332b6f8b8 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -48,11 +48,11 @@
 #define CPG_PLL_STBY_RESETB    BIT(0)
 #define CPG_PLL_STBY_RESETB_WEN        BIT(16)
 #define CPG_PLL_CLK1(x)                ((x) + 0x004)
-#define KDIV(val)              ((s16)FIELD_GET(GENMASK(31, 16), (val)))
-#define MDIV(val)              FIELD_GET(GENMASK(15, 6), (val))
-#define PDIV(val)              FIELD_GET(GENMASK(5, 0), (val))
+#define CPG_PLL_CLK1_KDIV(x)   ((s16)FIELD_GET(GENMASK(31, 16), (x)))
+#define CPG_PLL_CLK1_MDIV(x)   FIELD_GET(GENMASK(15, 6), (x))
+#define CPG_PLL_CLK1_PDIV(x)   FIELD_GET(GENMASK(5, 0), (x))
 #define CPG_PLL_CLK2(x)                ((x) + 0x008)
-#define SDIV(val)              FIELD_GET(GENMASK(2, 0), (val))
+#define CPG_PLL_CLK2_SDIV(x)   FIELD_GET(GENMASK(2, 0), (x))
 #define CPG_PLL_MON(x)         ((x) + 0x010)
 #define CPG_PLL_MON_RESETB     BIT(0)
 #define CPG_PLL_MON_LOCK       BIT(4)
@@ -210,10 +210,10 @@ static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
        clk1 = readl(priv->base + CPG_PLL_CLK1(pll.offset));
        clk2 = readl(priv->base + CPG_PLL_CLK2(pll.offset));
 
-       rate = mul_u64_u32_shr(parent_rate, (MDIV(clk1) << 16) + KDIV(clk1),
-                              16 + SDIV(clk2));
+       rate = mul_u64_u32_shr(parent_rate, (CPG_PLL_CLK1_MDIV(clk1) << 16) +
+                              CPG_PLL_CLK1_KDIV(clk1), 16 + CPG_PLL_CLK2_SDIV(clk2));
 
-       return DIV_ROUND_CLOSEST_ULL(rate, PDIV(clk1));
+       return DIV_ROUND_CLOSEST_ULL(rate, CPG_PLL_CLK1_PDIV(clk1));
 }
 
 static const struct clk_ops rzv2h_cpg_pll_ops = {