return true;
}
-static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_state,
- int pps, u32 *pps_val)
+static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ u32 val;
int ret;
- ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
+ ret = intel_dsc_read_pps_reg(crtc_state, pps, &val);
drm_WARN_ON(&i915->drm, !ret);
+
+ return val;
}
static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
u32 pps_temp;
/* PPS_0 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT;
vdsc_cfg->line_buf_depth =
vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
/* PPS_1 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
vdsc_cfg->bits_per_pixel = pps_temp;
crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
/* PPS_2 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances;
vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp);
/* PPS_3 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 3, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp);
vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp);
/* PPS_4 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 4, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
/* PPS_5 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 5, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
/* PPS_6 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 6, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
/* PPS_7 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 7, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
/* PPS_8 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 8, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp);
vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp);
/* PPS_9 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 9, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
/* PPS_10 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 10, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
/* PPS_16 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 16, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
if (DISPLAY_VER(i915) >= 14) {
/* PPS_17 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 17, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
/* PPS_18 */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 18, &pps_temp);
+ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);
vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp);