static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
int delay)
{
- int timeout = 1000;
+ int timeout = PCIE_LINK_RETRAIN_TIMEOUT_MS;
bool ret;
u16 lnk_status;
#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
+#define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
+
extern const unsigned char pcie_link_speed[];
extern bool pci_early_dump;
[POLICY_POWER_SUPERSAVE] = "powersupersave"
};
-#define LINK_RETRAIN_TIMEOUT HZ
-
/*
* The L1 PM substate capability is only implemented in function 0 in a
* multi function device.
* @pdev: Device whose link to wait for.
*
* Return TRUE if successful, or FALSE if training has not completed
- * within LINK_RETRAIN_TIMEOUT jiffies.
+ * within PCIE_LINK_RETRAIN_TIMEOUT_MS milliseconds.
*/
static bool pcie_wait_for_link_status(struct pci_dev *pdev)
{
unsigned long end_jiffies;
u16 lnksta;
- end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
+ end_jiffies = jiffies + msecs_to_jiffies(PCIE_LINK_RETRAIN_TIMEOUT_MS);
do {
pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
if (!(lnksta & PCI_EXP_LNKSTA_LT))