#include "z85230.h"
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/**
* z8530_read_port - Architecture specific interface function
* @p: port to read
* dread 5uS sanity delay.
*/
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static inline void z8530_write_port(unsigned long p, u8 d)
{
outb(d,Z8530_PORT_OF(p));
udelay(5);
}
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-
static void z8530_rx_done(struct z8530_channel *c);
static void z8530_tx_done(struct z8530_channel *c);
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/**
* read_zsreg - Read a register from a Z85230
* @c: Z8530 channel to read from (2 per chip)
if(reg)
z8530_write_port(c->ctrlio, reg);
z8530_write_port(c->ctrlio, val);
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}
/**
*
* Write directly to the data register on the Z8530
*/
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static inline void write_zsdata(struct z8530_channel *c, u8 val)
{
z8530_write_port(c->dataio, val);
* Register loading parameters for currently supported circuit types
*/
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/*
* Data clocked by telco end. This is the correct data for the UK
* "kilostream" service, and most other similar services.
if(stat&END_FR)
{
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/*
* Error ?
*/
write_zsctrl(c, RES_H_IUS);
}
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/**
* z8530_tx - Handle a PIO transmit event
* @c: Z8530 channel to process
}
}
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/*
* End of frame TX - fire another one
*/
if (chan->netdevice)
netif_carrier_off(chan->netdevice);
}
-
}
write_zsctrl(chan, RES_EXT_INT);
write_zsctrl(chan, RES_H_IUS);
chan->status=status;
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if(chan->dma_tx)
{
if(status&TxEOM)
* (eg the MacII) we must clear the interrupt cause or die.
*/
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static void z8530_rx_clear(struct z8530_channel *c)
{
/*
.status = z8530_status_clear,
};
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EXPORT_SYMBOL(z8530_nop);
/**
while(++work<5000)
{
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intr = read_zsreg(&dev->chanA, R3);
if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT)))
break;
0x55,0,0,0
};
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/**
* z8530_sync_open - Open a Z8530 channel for PIO
* @dev: The network interface we are using
return 0;
}
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EXPORT_SYMBOL(z8530_sync_open);
/**
c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2;
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spin_lock_irqsave(c->lock, cflags);
/*
unsigned long dflags, cflags;
u8 chk;
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spin_lock_irqsave(c->lock, cflags);
c->irqs = &z8530_nop;
return 0;
}
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EXPORT_SYMBOL(z8530_sync_txdma_close);
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/*
* Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny
* it exists...
return ret;
}
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EXPORT_SYMBOL(z8530_init);
/**
EXPORT_SYMBOL(z8530_channel_load);
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/**
* z8530_tx_begin - Begin packet transmission
* @c: The Z8530 channel to kick
else
{
c->txcount=c->tx_skb->len;
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-
+
if(c->dma_tx)
{
/*
}
else
{
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/* ABUNDER off */
write_zsreg(c, R10, c->regs[10]);
write_zsctrl(c, RES_Tx_CRC);
write_zsreg(c, R8, *c->tx_ptr++);
c->txcount--;
}
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}
}
/*
/*
* Is our receive engine in DMA mode
*/
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if(c->rxdma_on)
{
/*
* Save the ready state and the buffer currently
* being used as the DMA target
*/
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int ready=c->dma_ready;
unsigned char *rxb=c->rx_buf[c->dma_num];
unsigned long flags;
/*
* Complete this DMA. Necessary to find the length
*/
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flags=claim_dma_lock();
disable_dma(c->rxdma);
if(c->tx_next_skb)
return NETDEV_TX_BUSY;
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/* PC SPECIFIC - DMA limits */
/*