arm64: dts: imx93: add cache info

i.MX93 features two Cortex-A55 cores with per core L1 Instruction
cache size 32KB, L1 data cache size 32KB, per core L2 cache 64KB, and
unified 256KB L3 cache.

Add the cache info to remove cacheinfo warnings at boot:
"cacheinfo: Unable to detect cache hierarchy for CPU 0"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index e8fd008d6333c0aa91c2801a2ac1559d2b183971..928761aa5a7583e393d31124edff8ce9047a98f2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -69,6 +69,13 @@
                        enable-method = "psci";
                        #cooling-cells = <2>;
                        cpu-idle-states = <&cpu_pd_wait>;
+                       i-cache-size = <32768>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <128>;
+                       d-cache-size = <32768>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&l2_cache_l0>;
                };
 
                A55_1: cpu@100 {
@@ -78,8 +85,43 @@
                        enable-method = "psci";
                        #cooling-cells = <2>;
                        cpu-idle-states = <&cpu_pd_wait>;
+                       i-cache-size = <32768>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <128>;
+                       d-cache-size = <32768>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&l2_cache_l1>;
                };
 
+               l2_cache_l0: l2-cache-l0 {
+                       compatible = "cache";
+                       cache-size = <65536>;
+                       cache-line-size = <64>;
+                       cache-sets = <256>;
+                       cache-level = <2>;
+                       cache-unified;
+                       next-level-cache = <&l3_cache>;
+               };
+
+               l2_cache_l1: l2-cache-l1 {
+                       compatible = "cache";
+                       cache-size = <65536>;
+                       cache-line-size = <64>;
+                       cache-sets = <256>;
+                       cache-level = <2>;
+                       cache-unified;
+                       next-level-cache = <&l3_cache>;
+               };
+
+               l3_cache: l3-cache {
+                       compatible = "cache";
+                       cache-size = <262144>;
+                       cache-line-size = <64>;
+                       cache-sets = <256>;
+                       cache-level = <3>;
+                       cache-unified;
+               };
        };
 
        osc_32k: clock-osc-32k {