ARM: dts: rockchip: Split up rgmii1 pinctrl on rv1126

Split up the pinctrl definitions for rgmii1 so it can be shared
with devices using an RMII PHY.

Signed-off-by: Tim Lunn <tim@feathertop.org>
Link: https://lore.kernel.org/r/20231203124004.2676174-6-tim@feathertop.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts
index f09be840596454d38378e0ab5006790a421ed6bb..0c2396b8f8db6db18b3ed78e2df2b358b8d2c493 100644 (file)
--- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts
+++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts
@@ -61,7 +61,7 @@
        phy-mode = "rgmii";
        phy-supply = <&vcc_3v3>;
        pinctrl-names = "default";
-       pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>;
+       pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>;
        tx_delay = <0x2a>;
        rx_delay = <0x1a>;
        status = "okay";

diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
index 167a48afa3a48d2912bfa2325de8aa3992c7db2e..06b1d7f2d8585a5a99d4a4fd65f4f3741d9fe6e1 100644 (file)
--- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
@@ -115,36 +115,56 @@
        };
        rgmii {
                /omit-if-no-ref/
-               rgmiim1_pins: rgmiim1-pins {
+               rgmiim1_miim: rgmiim1-miim {
                        rockchip,pins =
                                /* rgmii_mdc_m1 */
                                <2 RK_PC2 2 &pcfg_pull_none>,
                                /* rgmii_mdio_m1 */
-                               <2 RK_PC1 2 &pcfg_pull_none>,
-                               /* rgmii_rxclk_m1 */
-                               <2 RK_PD3 2 &pcfg_pull_none>,
+                               <2 RK_PC1 2 &pcfg_pull_none>;
+               };
+               /omit-if-no-ref/
+               rgmiim1_rxer: rgmiim1-rxer {
+                       rockchip,pins =
+                               /* rgmii_rxer_m1 */
+                               <2 RK_PC0 2 &pcfg_pull_none>;
+               };
+               /omit-if-no-ref/
+               rgmiim1_bus2: rgmiim1-bus2 {
+                       rockchip,pins =
                                /* rgmii_rxd0_m1 */
                                <2 RK_PB5 2 &pcfg_pull_none>,
                                /* rgmii_rxd1_m1 */
                                <2 RK_PB6 2 &pcfg_pull_none>,
-                               /* rgmii_rxd2_m1 */
-                               <2 RK_PC7 2 &pcfg_pull_none>,
-                               /* rgmii_rxd3_m1 */
-                               <2 RK_PD0 2 &pcfg_pull_none>,
                                /* rgmii_rxdv_m1 */
                                <2 RK_PB4 2 &pcfg_pull_none>,
-                               /* rgmii_txclk_m1 */
-                               <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
                                /* rgmii_txd0_m1 */
                                <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
                                /* rgmii_txd1_m1 */
                                <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
+                               /* rgmii_txen_m1 */
+                               <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
+               };
+               /omit-if-no-ref/
+               rgmiim1_bus4: rgmiim1-bus4 {
+                       rockchip,pins =
+                               /* rgmii_rxclk_m1 */
+                               <2 RK_PD3 2 &pcfg_pull_none>,
+                               /* rgmii_rxd2_m1 */
+                               <2 RK_PC7 2 &pcfg_pull_none>,
+                               /* rgmii_rxd3_m1 */
+                               <2 RK_PD0 2 &pcfg_pull_none>,
+                               /* rgmii_txclk_m1 */
+                               <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
                                /* rgmii_txd2_m1 */
                                <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
                                /* rgmii_txd3_m1 */
-                               <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>,
-                               /* rgmii_txen_m1 */
-                               <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
+                               <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>;
+               };
+               /omit-if-no-ref/
+               rgmiim1_mclkinout: rgmiim1-mclkinout {
+                       rockchip,pins =
+                               /* rgmii_clk_m1 */
+                               <2 RK_PB7 2 &pcfg_pull_none>;
                };
        };
        sdmmc0 {