depends on ARCH_MEDIATEK || COMPILE_TEST
config COMMON_CLK_MEDIATEK
- bool
+ tristate
select RESET_CONTROLLER
help
MediaTek SoCs' clock support.
*/
#include <linux/delay.h>
+#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/slab.h>
return clk;
}
+
+MODULE_LICENSE("GPL");
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
+#include <linux/module.h>
#include <linux/slab.h>
#include "clk-mtk.h"
return 0;
}
+
+MODULE_LICENSE("GPL");
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/clkdev.h>
+#include <linux/module.h>
#include "clk-mtk.h"
#include "clk-gate.h"
.enable = mtk_cg_enable,
.disable = mtk_cg_disable,
};
+EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr);
const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
.is_enabled = mtk_cg_bit_is_set,
.enable = mtk_cg_enable_inv,
.disable = mtk_cg_disable_inv,
};
+EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_inv);
const struct clk_ops mtk_clk_gate_ops_no_setclr = {
.is_enabled = mtk_cg_bit_is_cleared,
.enable = mtk_cg_enable_no_setclr,
.disable = mtk_cg_disable_no_setclr,
};
+EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr);
const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
.is_enabled = mtk_cg_bit_is_set,
.enable = mtk_cg_enable_inv_no_setclr,
.disable = mtk_cg_disable_inv_no_setclr,
};
+EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
struct clk *mtk_clk_register_gate(
const char *name,
return clk;
}
+EXPORT_SYMBOL_GPL(mtk_clk_register_gate);
+
+MODULE_LICENSE("GPL");
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/clkdev.h>
+#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/device.h>
#include <linux/of_device.h>
return NULL;
}
+EXPORT_SYMBOL_GPL(mtk_alloc_clk_data);
void mtk_free_clk_data(struct clk_onecell_data *clk_data)
{
clk_data->clks[rc->id] = clk;
}
}
+EXPORT_SYMBOL_GPL(mtk_clk_register_fixed_clks);
void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
int num, struct clk_onecell_data *clk_data)
clk_data->clks[ff->id] = clk;
}
}
+EXPORT_SYMBOL_GPL(mtk_clk_register_factors);
int mtk_clk_register_gates_with_dev(struct device_node *node,
const struct mtk_gate *clks,
return mtk_clk_register_gates_with_dev(node,
clks, num, clk_data, NULL);
}
+EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
void __iomem *base, spinlock_t *lock)
clk_data->clks[mc->id] = clk;
}
}
+EXPORT_SYMBOL_GPL(mtk_clk_register_composites);
void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
int num, void __iomem *base, spinlock_t *lock,
mtk_free_clk_data(clk_data);
return r;
}
+
+MODULE_LICENSE("GPL");
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
+#include <linux/module.h>
#include "clk-mtk.h"
#include "clk-mux.h"
return 0;
}
+EXPORT_SYMBOL_GPL(mtk_clk_register_muxes);
+
+MODULE_LICENSE("GPL");
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/io.h>
+#include <linux/module.h>
#include <linux/slab.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
clk_data->clks[pll->id] = clk;
}
}
+EXPORT_SYMBOL_GPL(mtk_clk_register_plls);
+
+MODULE_LICENSE("GPL");
mtk_register_reset_controller_common(np, num_regs, regofs,
&mtk_reset_ops_set_clr);
}
+
+MODULE_LICENSE("GPL");