drm/amdgpu/mes12: add API for user queue reset

Add API for resetting user queues.

Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 35cd6ad73912df38990e5fd736ce9aa2672c0222..47a73f6ae4dae9eb9e07becfd9967fd1e92db369 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -350,6 +350,32 @@ static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes,
                        offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 }
 
+static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes,
+                                   struct mes_reset_queue_input *input)
+{
+       union MESAPI__RESET mes_reset_queue_pkt;
+       int pipe;
+
+       memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
+
+       mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
+       mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
+       mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+
+       mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
+       mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr;
+       /*mes_reset_queue_pkt.reset_queue_only = 1;*/
+
+       if (mes->adev->enable_uni_mes)
+               pipe = AMDGPU_MES_KIQ_PIPE;
+       else
+               pipe = AMDGPU_MES_SCHED_PIPE;
+
+       return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
+                       &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
+                       offsetof(union MESAPI__REMOVE_QUEUE, api_status));
+}
+
 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes,
                                      struct mes_map_legacy_queue_input *input)
 {
@@ -723,6 +749,7 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = {
        .resume_gang = mes_v12_0_resume_gang,
        .misc_op = mes_v12_0_misc_op,
        .reset_legacy_queue = mes_v12_0_reset_legacy_queue,
+       .reset_hw_queue = mes_v12_0_reset_hw_queue,
 };
 
 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,