drm/amd/pm: correct platformcaps setup

Correct Polaris10 platformcaps setup.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c
index 68a7aed16196df8af1df44fadeb2d56298c826f8..739e215ec8b7fc3c05f3e1f2576e06e320b98c9c 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c
@@ -486,9 +486,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
        phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                        PHM_PlatformCaps_AutomaticDCTransition);
 
-       if (hwmgr->chip_id != CHIP_POLARIS10)
+       if (((hwmgr->chip_id == CHIP_POLARIS11) && !hwmgr->is_kicker) ||
+           (hwmgr->chip_id == CHIP_POLARIS12))
                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-                                       PHM_PlatformCaps_SPLLShutdownSupport);
+                               PHM_PlatformCaps_SPLLShutdownSupport);
 
        if (hwmgr->chip_id != CHIP_POLARIS11) {
                phm_cap_set(hwmgr->platform_descriptor.platformCaps,

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 79dea9329b2a9155187915aec7a8867fdd97310d..122b15dc76e1710f2d3fa58f26ebecbecdd6cadb 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1823,6 +1823,17 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
                phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_EngineSpreadSpectrumSupport);
        }
+
+       if ((adev->pdev->device == 0x699F) &&
+           (adev->pdev->revision == 0xCF)) {
+               phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_PowerContainment);
+               data->enable_tdc_limit_feature = false;
+               data->enable_pkg_pwr_tracking_feature = false;
+               data->disable_edc_leakage_controller = true;
+               phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                                       PHM_PlatformCaps_ClockStretcher);
+       }
 }
 
 static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
index 997b996b25bf69bd3e8df1bbdac961b79aaa1445..8176b855b9df3cc99573ebd0cce01281bc3fb1cd 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
@@ -2041,8 +2041,11 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
        if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
                        &gpio_pin)) {
                table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
-               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-                               PHM_PlatformCaps_AutomaticDCTransition);
+               if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_AutomaticDCTransition) &&
+                   !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme, NULL))
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                                       PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
        } else {
                table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
                phm_cap_unset(hwmgr->platform_descriptor.platformCaps,