drm/amdgpu: extent threshold of waiting FLR_COMPLETE
authorMonk Liu <Monk.Liu@amd.com>
Tue, 21 Apr 2020 10:04:50 +0000 (18:04 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 24 Apr 2020 15:42:11 +0000 (11:42 -0400)
to 5s to satisfy WHOLE GPU reset which need 3+ seconds to
finish

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Yintian Tao <yttao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h

index 52a697545801650212c1b7b745da7b9305e81224..83b453f5d7176616df5f78346422a2c8197e2bfc 100644 (file)
@@ -26,7 +26,7 @@
 
 #define AI_MAILBOX_POLL_ACK_TIMEDOUT   500
 #define AI_MAILBOX_POLL_MSG_TIMEDOUT   12000
-#define AI_MAILBOX_POLL_FLR_TIMEDOUT   500
+#define AI_MAILBOX_POLL_FLR_TIMEDOUT   5000
 
 enum idh_request {
        IDH_REQ_GPU_INIT_ACCESS = 1,
index 45bcf438e6070632fad51a6a2f9bf7816caad496..52605e14a1a530457f0a41b3577a29efc6ba56b1 100644 (file)
@@ -26,7 +26,7 @@
 
 #define NV_MAILBOX_POLL_ACK_TIMEDOUT   500
 #define NV_MAILBOX_POLL_MSG_TIMEDOUT   6000
-#define NV_MAILBOX_POLL_FLR_TIMEDOUT   500
+#define NV_MAILBOX_POLL_FLR_TIMEDOUT   5000
 
 enum idh_request {
        IDH_REQ_GPU_INIT_ACCESS = 1,