soc: aspeed: Re-enable FWH2AHB on AST2600

Recent builds of the vendor u-boot tree disable features of the
BMC that may allow unwanted access if not correctly configured. This
includes the firmware hub to ahb bridge (FWH2AHB), which is used by this
driver.

The bit to "un-disable" it is in the SCU. Set it only when the ioctl is
called and we are running on the ast2600, as to not open up the
'backdoor' unless there's userspace trying to use it.

Fixes: deb50313ba83 ("soc: aspeed-lpc-ctrl: LPC to AHB mapping on ast2600")
Link: https://lore.kernel.org/r/20210629073520.318514-2-joel@jms.id.au
Signed-off-by: Joel Stanley <joel@jms.id.au>

diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
index 55e46fa6cf42413d2645ff5024e729845dabf833..6893c5ec3259d12a391730c9b263714f8d67794a 100644 (file)
--- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c
+++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
@@ -37,6 +37,7 @@ struct aspeed_lpc_ctrl {
        u32                     pnor_size;
        u32                     pnor_base;
        bool                    fwh2ahb;
+       struct regmap           *scu;
 };
 
 static struct aspeed_lpc_ctrl *file_aspeed_lpc_ctrl(struct file *file)
@@ -183,13 +184,22 @@ static long aspeed_lpc_ctrl_ioctl(struct file *file, unsigned int cmd,
 
                /*
                 * Switch to FWH2AHB mode, AST2600 only.
-                *
-                * The other bits in this register are interrupt status bits
-                * that are cleared by writing 1. As we don't want to clear
-                * them, set only the bit of interest.
                 */
-               if (lpc_ctrl->fwh2ahb)
+               if (lpc_ctrl->fwh2ahb) {
+                       /*
+                        * Enable FWH2AHB in SCU debug control register 2. This
+                        * does not turn it on, but makes it available for it
+                        * to be configured in HICR6.
+                        */
+                       regmap_update_bits(lpc_ctrl->scu, 0x0D8, BIT(2), 0);
+
+                       /*
+                        * The other bits in this register are interrupt status bits
+                        * that are cleared by writing 1. As we don't want to clear
+                        * them, set only the bit of interest.
+                        */
                        regmap_write(lpc_ctrl->regmap, HICR6, SW_FWH2AHB);
+               }
 
                /*
                 * Enable LPC FHW cycles. This is required for the host to
@@ -296,9 +306,16 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
                return rc;
        }
 
-       if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-lpc-ctrl"))
+       if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-lpc-ctrl")) {
                lpc_ctrl->fwh2ahb = true;
 
+               lpc_ctrl->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2600-scu");
+               if (IS_ERR(lpc_ctrl->scu)) {
+                       dev_err(dev, "couldn't find scu\n");
+                       return PTR_ERR(lpc_ctrl->scu);
+               }
+       }
+
        lpc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR;
        lpc_ctrl->miscdev.name = DEVICE_NAME;
        lpc_ctrl->miscdev.fops = &aspeed_lpc_ctrl_fops;