arm64: dts: imx8mp: Fix pgc vpu locations

The various pgv_vpu nodes have a mismatch between the value after
the @ symbol and what is referenced by 'reg' so reorder the nodes
to align.

Fixes: df680992dd62 ("arm64: dts: imx8mp: add vpu pgc nodes")
Suggested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewd-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 8928a84689a8cc911113dd06dde0f1360b60c043..5e7360218d202f670ac2acf38ed47921e643a7c4 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -838,6 +838,12 @@
                                                assigned-clock-rates = <800000000>, <400000000>;
                                        };
 
+                                       pgc_vpumix: power-domain@8 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
+                                               clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
+                                       };
+
                                        pgc_gpu3d: power-domain@9 {
                                                #power-domain-cells = <0>;
                                                reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
@@ -853,6 +859,28 @@
                                                         <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
                                        };
 
+                                       pgc_vpu_g1: power-domain@11 {
+                                               #power-domain-cells = <0>;
+                                               power-domains = <&pgc_vpumix>;
+                                               reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
+                                               clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
+                                       };
+
+                                       pgc_vpu_g2: power-domain@12 {
+                                               #power-domain-cells = <0>;
+                                               power-domains = <&pgc_vpumix>;
+                                               reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
+                                               clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
+
+                                       };
+
+                                       pgc_vpu_vc8000e: power-domain@13 {
+                                               #power-domain-cells = <0>;
+                                               power-domains = <&pgc_vpumix>;
+                                               reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
+                                               clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
+                                       };
+
                                        pgc_hdmimix: power-domain@14 {
                                                #power-domain-cells = <0>;
                                                reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
@@ -890,33 +918,6 @@
                                                reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
                                                clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
                                        };
-
-                                       pgc_vpumix: power-domain@19 {
-                                               #power-domain-cells = <0>;
-                                               reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
-                                               clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
-                                       };
-
-                                       pgc_vpu_g1: power-domain@20 {
-                                               #power-domain-cells = <0>;
-                                               power-domains = <&pgc_vpumix>;
-                                               reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
-                                               clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
-                                       };
-
-                                       pgc_vpu_g2: power-domain@21 {
-                                               #power-domain-cells = <0>;
-                                               power-domains = <&pgc_vpumix>;
-                                               reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
-                                               clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
-                                       };
-
-                                       pgc_vpu_vc8000e: power-domain@22 {
-                                               #power-domain-cells = <0>;
-                                               power-domains = <&pgc_vpumix>;
-                                               reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
-                                               clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
-                                       };
                                };
                        };
                };