arm64: dts: ti: k3-am69-sk: Add PCIe support

The AM69-SK board has 3 instances of PCIe namely PCIe0, PCIe1 and PCIe3.
The x4 PCIe0 instance is connected to a Card Edge connector via SERDES1.
The x2 PCIe1 instance is connected to an M.2 M Key connector via SERDES0.
The x1 PCIe3 instance is connected to an M.2 E Key connector via SERDES0.

Add device-tree support for enabling all 3 PCIe instances in Root-Complex
mode of operation.

Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20240529082259.1619695-5-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
index 6b301efbd1b511af136ffcc0452e8f5f56fc3a56..3f655852244ee7147e97c5138fbcf1804d4b8d27 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
@@ -1224,3 +1224,65 @@
                };
        };
 };
+
+&serdes_ln_ctrl {
+       idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+                     <J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_USB>,
+                       <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+                       <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>;
+};
+
+&serdes_wiz0 {
+       status = "okay";
+};
+
+&serdes0 {
+       status = "okay";
+
+       serdes0_pcie_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <3>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>;
+       };
+};
+
+&serdes_wiz1 {
+       status = "okay";
+};
+
+&serdes1 {
+       status = "okay";
+
+       serdes1_pcie_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <4>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, <&serdes_wiz1 3>, <&serdes_wiz1 4>;
+       };
+};
+
+&pcie0_rc {
+       status = "okay";
+       reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes1_pcie_link>;
+       phy-names = "pcie-phy";
+};
+
+&pcie1_rc {
+       status = "okay";
+       reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <2>;
+};
+
+&pcie3_rc {
+       status = "okay";
+       reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <1>;
+};