Merge patch series "riscv: Add bfloat16 instruction support"

Inochi Amaoto <inochiama@gmail.com> says:

Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.

* patches from https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com:
  riscv: hwprobe: export bfloat16 ISA extension
  riscv: add ISA extension parsing for bfloat16 ISA extension
  dt-bindings: riscv: add bfloat16 ISA extension description

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com

diff --cc Documentation/arch/riscv/hwprobe.rst
Simple merge

diff --cc Documentation/devicetree/bindings/riscv/extensions.yaml
Simple merge

diff --cc arch/riscv/include/uapi/asm/hwprobe.h
index 8cac35cb19d8b154ba117ca924f77e4c4b46c0ed,aecc1c800d54bf336eb8e56aa74cc55c98e20673..08ab52fe8004e0291d623206d91cf709ce12ce59
--- 1/arch/riscv/include/uapi/asm/hwprobe.h
--- 2/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@@ -73,8 -73,9 +73,11 @@@ struct riscv_hwprobe 
  #define               RISCV_HWPROBE_EXT_ZCMOP         (1ULL << 47)
  #define               RISCV_HWPROBE_EXT_ZAWRS         (1ULL << 48)
  #define               RISCV_HWPROBE_EXT_SUPM          (1ULL << 49)
 -#define               RISCV_HWPROBE_EXT_ZFBFMIN       (1ULL << 50)
 -#define               RISCV_HWPROBE_EXT_ZVFBFMIN      (1ULL << 51)
 -#define               RISCV_HWPROBE_EXT_ZVFBFWMA      (1ULL << 52)
 +#define               RISCV_HWPROBE_EXT_ZICNTR        (1ULL << 50)
 +#define               RISCV_HWPROBE_EXT_ZIHPM         (1ULL << 51)
++#define               RISCV_HWPROBE_EXT_ZFBFMIN       (1ULL << 52)
++#define               RISCV_HWPROBE_EXT_ZVFBFMIN      (1ULL << 53)
++#define               RISCV_HWPROBE_EXT_ZVFBFWMA      (1ULL << 54)
  #define RISCV_HWPROBE_KEY_CPUPERF_0   5
  #define               RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
  #define               RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)

diff --cc arch/riscv/kernel/cpufeature.c
Simple merge

diff --cc arch/riscv/kernel/sys_hwprobe.c
Simple merge