drm/i915: use 32-bit access for gen2 irq registers

We've previously switched from 16-bit to 32-bit access for gen2 irq
registers, but one was left behind. Fix it.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/5a56286c94e08a02435c60ce0fbff13aca6c0d1f.1744630147.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 819ab933bb1055a576f0839cbf72ef30ff635200..df16c2b86b9da6bdb30203a54f3c8f4f8a012b01 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1782,8 +1782,6 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt)
                gt->ier = intel_uncore_read(uncore, VLV_IER);
        else if (HAS_PCH_SPLIT(i915))
                gt->ier = intel_uncore_read(uncore, DEIER);
-       else if (GRAPHICS_VER(i915) == 2)
-               gt->ier = intel_uncore_read16(uncore, GEN2_IER);
        else
                gt->ier = intel_uncore_read(uncore, GEN2_IER);
 }