drm/amdgpu/mes: use correct MES pipe for resets
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 29 Apr 2025 19:27:20 +0000 (15:27 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 30 Apr 2025 22:16:14 +0000 (18:16 -0400)
Use the KIQ pipe for kernel queues and the SCHED pipe for
user queues.

Fixes: 2408b0272b04 ("drm/amdgpu/mes: consolidate on a single mes reset callback")
Cc: Michael Chen <Michael.Chen@amd.com>
Cc: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

index 5de0d6c528f4e49f62c22fb57e9a89bb49a96fab..2febb63ab2322668d41e1c899a2919110c99f127 100644 (file)
@@ -349,6 +349,7 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
        queue_input.wptr_addr = ring->wptr_gpu_addr;
        queue_input.vmid = vmid;
        queue_input.use_mmio = use_mmio;
+       queue_input.is_kq = true;
        if (ring->funcs->type == AMDGPU_RING_TYPE_GFX)
                queue_input.legacy_gfx = true;
 
index e98b0d892a593e7314938cec341f02f8096c1777..a41f65b4f733a51e8e9c9a4bed718de593d55a0c 100644 (file)
@@ -277,6 +277,7 @@ struct mes_reset_queue_input {
        uint64_t                           wptr_addr;
        uint32_t                           vmid;
        bool                               legacy_gfx;
+       bool                               is_kq;
 };
 
 enum mes_misc_opcode {
index f9f2fbc0a7166113be7f5d3040fbd7638fa9f68e..b4f17332d46643e33b61e4e9558b5253feb66e9e 100644 (file)
@@ -869,7 +869,7 @@ static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes,
                mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
        }
 
-       if (mes->adev->enable_uni_mes)
+       if (input->is_kq)
                pipe = AMDGPU_MES_KIQ_PIPE;
        else
                pipe = AMDGPU_MES_SCHED_PIPE;