drm/amdgpu: set snoop bit in pde/pte entries for A+A

Page tables in vram mapping to cpu is changed from uncached to
cached in A+A, the snoop bit in VM_CONTEXTx_PAGE_TABLE_BASE_ADDR/
PDE0s/PDE1s/PDE2s/PTE.TFs has to be set so gpuvm walker snoop
page table data out of CPU cache.

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c5fea144b759d5db0677fb37c337f5dfa241de0f..feed820091f6fb6710bc961768fb9f774802f769 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1432,6 +1432,10 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
                        flags |= AMDGPU_PTE_SNOOPED;
        }
 
+       if (mem && mem->mem_type == TTM_PL_VRAM &&
+                       mem->bus.caching == ttm_cached)
+               flags |= AMDGPU_PTE_SNOOPED;
+
        return flags;
 }