drm/i915: move DDI_CLK_VALFREQ next to other Cx0 PHY registers
authorJani Nikula <jani.nikula@intel.com>
Fri, 13 Dec 2024 11:51:11 +0000 (13:51 +0200)
committerJani Nikula <jani.nikula@intel.com>
Mon, 16 Dec 2024 12:20:02 +0000 (14:20 +0200)
Relocate DDI_CLK_VALFREQ register definition next to other Cx0 PHY
register macros.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241213115111.335474-3-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
drivers/gpu/drm/i915/i915_reg.h

index f0e5c196eae4cf038b21bb088bafbc4254ca46a7..87d52b309608762805fc96212f9493f67c9c9ab0 100644 (file)
@@ -9,6 +9,11 @@
 #include "i915_reg_defs.h"
 #include "intel_display_limits.h"
 
+/* DDI Buffer Control */
+#define _DDI_CLK_VALFREQ_A             0x64030
+#define _DDI_CLK_VALFREQ_B             0x64130
+#define DDI_CLK_VALFREQ(port)          _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
+
 /*
  * Wrapper macro to convert from port number to the index used in some of the
  * registers. For Display version 20 and above it converts the port number to a
index 33cfe07a9b2e6c037058e0ba7b4a7600a60b08d8..765e6c0528fb0b5a894395b77a5edbf0b0c80009 100644 (file)
 #define CLKGATE_DIS_PSL_EXT(pipe) \
        _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
 
-/* DDI Buffer Control */
-#define _DDI_CLK_VALFREQ_A             0x64030
-#define _DDI_CLK_VALFREQ_B             0x64130
-#define DDI_CLK_VALFREQ(port)          _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
-
 /*
  * Display engine regs
  */