x86/platform/intel-mid: Switch to new Intel CPU model defines

New CPU #defines encode vendor and family as well as model.

N.B. Drop Haswell. CPU model 0x3C was included by mistake
in upstream code.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Acked-by: Andy Shevchenko <andy@kernel.org>
Link: https://lore.kernel.org/all/20240521161002.12866-1-tony.luck%40intel.com

diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 7be71c2cdc83ee5f73414a3f22c45c62d59e2970..f83bbe0acd4a1b1e47264c65713132cd4cc2c9f9 100644 (file)
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -22,6 +22,7 @@
 #include <asm/mpspec_def.h>
 #include <asm/hw_irq.h>
 #include <asm/apic.h>
+#include <asm/cpu_device_id.h>
 #include <asm/io_apic.h>
 #include <asm/intel-mid.h>
 #include <asm/io.h>
@@ -55,9 +56,8 @@ static void __init intel_mid_time_init(void)
 
 static void intel_mid_arch_setup(void)
 {
-       switch (boot_cpu_data.x86_model) {
-       case 0x3C:
-       case 0x4A:
+       switch (boot_cpu_data.x86_vfm) {
+       case INTEL_ATOM_SILVERMONT_MID:
                x86_platform.legacy.rtc = 1;
                break;
        default: