drm/amd/powerplay: add the hw manager for vega12 (v4)
authorEvan Quan <evan.quan@amd.com>
Mon, 19 Mar 2018 19:23:57 +0000 (14:23 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 21 Mar 2018 19:36:56 +0000 (14:36 -0500)
handles the driver power state setup

v2: squash in the following:
- handle negative temperature ranges
- add vega12 thermal ranges
- use ffs/fls
- remove ACG code
- resend NumOfDisplays message
- correct max dpm levels
- remove power containment settings
- fix warnings
- add sensors interface
- delete unused overdrive arbiter
- drop get_temperature callback
- smu table cleanup
- atomfirmware smu dpm table updates
v3: rebase
v4: rebase

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
13 files changed:
drivers/gpu/drm/amd/include/dm_pp_interface.h
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_powertune.c [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_powertune.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

index 721473199921154b51c37ebf9236a25b0664ca06..7852952d1fdee3bce1dcc79e64d4a83ddeca4057 100644 (file)
@@ -23,7 +23,7 @@
 #ifndef _DM_PP_INTERFACE_
 #define _DM_PP_INTERFACE_
 
-#define PP_MAX_CLOCK_LEVELS 8
+#define PP_MAX_CLOCK_LEVELS 16
 
 enum amd_pp_display_config_type{
        AMD_PP_DisplayConfigType_None = 0,
index c1249e03c91241de511be257d662862b63a0291f..9446dbc47551cf85b677f947f4e42cababdbfb70 100644 (file)
@@ -31,7 +31,9 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
                smu7_clockpowergating.o \
                vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \
                vega10_thermal.o smu10_hwmgr.o pp_psm.o\
-               pp_overdriver.o smu_helper.o pp_psm_legacy.o pp_psm_new.o
+               pp_overdriver.o smu_helper.o pp_psm_legacy.o pp_psm_new.o \
+               vega12_processpptables.o vega12_hwmgr.o \
+               vega12_powertune.o vega12_thermal.o
 
 AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
 
index 229030027f3ecd45a35fd2577cd428fcea980e9e..8f032e6938421567a5bb9255f0ad5508a5ce416b 100644 (file)
@@ -41,11 +41,13 @@ extern const struct pp_smumgr_func tonga_smu_funcs;
 extern const struct pp_smumgr_func fiji_smu_funcs;
 extern const struct pp_smumgr_func polaris10_smu_funcs;
 extern const struct pp_smumgr_func vega10_smu_funcs;
+extern const struct pp_smumgr_func vega12_smu_funcs;
 extern const struct pp_smumgr_func smu10_smu_funcs;
 
 extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
 extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
 extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
+extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
 extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
 
 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
@@ -186,6 +188,10 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
                        hwmgr->smumgr_funcs = &vega10_smu_funcs;
                        vega10_hwmgr_init(hwmgr);
                        break;
+               case CHIP_VEGA12:
+                       hwmgr->smumgr_funcs = &vega12_smu_funcs;
+                       vega12_hwmgr_init(hwmgr);
+                       break;
                default:
                        return -EINVAL;
                }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
new file mode 100644 (file)
index 0000000..66633b6
--- /dev/null
@@ -0,0 +1,2444 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include "hwmgr.h"
+#include "amd_powerplay.h"
+#include "vega12_smumgr.h"
+#include "hardwaremanager.h"
+#include "ppatomfwctrl.h"
+#include "atomfirmware.h"
+#include "cgs_common.h"
+#include "vega12_powertune.h"
+#include "vega12_inc.h"
+#include "pp_soc15.h"
+#include "pppcielanes.h"
+#include "vega12_hwmgr.h"
+#include "vega12_processpptables.h"
+#include "vega12_pptable.h"
+#include "vega12_thermal.h"
+#include "vega12_ppsmc.h"
+#include "pp_debug.h"
+#include "amd_pcie_helpers.h"
+#include "cgs_linux.h"
+#include "ppinterrupt.h"
+#include "pp_overdriver.h"
+#include "pp_thermal.h"
+
+static const ULONG PhwVega12_Magic = (ULONG)(PHM_VIslands_Magic);
+
+static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
+               enum pp_clock_type type, uint32_t mask);
+static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
+               uint32_t *clock,
+               PPCLK_e clock_select,
+               bool max);
+
+struct vega12_power_state *cast_phw_vega12_power_state(
+                                 struct pp_hw_power_state *hw_ps)
+{
+       PP_ASSERT_WITH_CODE((PhwVega12_Magic == hw_ps->magic),
+                               "Invalid Powerstate Type!",
+                                return NULL;);
+
+       return (struct vega12_power_state *)hw_ps;
+}
+
+const struct vega12_power_state *cast_const_phw_vega12_power_state(
+                                const struct pp_hw_power_state *hw_ps)
+{
+       PP_ASSERT_WITH_CODE((PhwVega12_Magic == hw_ps->magic),
+                               "Invalid Powerstate Type!",
+                                return NULL;);
+
+       return (const struct vega12_power_state *)hw_ps;
+}
+
+static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+
+       data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT;
+       data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT;
+       data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT;
+       data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT;
+       data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT;
+
+       data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT;
+       data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+       data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+       data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+       data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+       data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+       data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+       data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+       data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+       data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+       data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+       data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+       data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
+
+       data->registry_data.disallowed_features = 0x0;
+       data->registry_data.od_state_in_dc_support = 0;
+       data->registry_data.skip_baco_hardware = 0;
+
+       data->registry_data.log_avfs_param = 0;
+       data->registry_data.sclk_throttle_low_notification = 1;
+       data->registry_data.force_dpm_high = 0;
+       data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
+
+       data->registry_data.didt_support = 0;
+       if (data->registry_data.didt_support) {
+               data->registry_data.didt_mode = 6;
+               data->registry_data.sq_ramping_support = 1;
+               data->registry_data.db_ramping_support = 0;
+               data->registry_data.td_ramping_support = 0;
+               data->registry_data.tcp_ramping_support = 0;
+               data->registry_data.dbr_ramping_support = 0;
+               data->registry_data.edc_didt_support = 1;
+               data->registry_data.gc_didt_support = 0;
+               data->registry_data.psm_didt_support = 0;
+       }
+
+       data->registry_data.pcie_lane_override = 0xff;
+       data->registry_data.pcie_speed_override = 0xff;
+       data->registry_data.pcie_clock_override = 0xffffffff;
+       data->registry_data.regulator_hot_gpio_support = 1;
+       data->registry_data.ac_dc_switch_gpio_support = 0;
+       data->registry_data.quick_transition_support = 0;
+       data->registry_data.zrpm_start_temp = 0xffff;
+       data->registry_data.zrpm_stop_temp = 0xffff;
+       data->registry_data.odn_feature_enable = 1;
+       data->registry_data.disable_water_mark = 0;
+       data->registry_data.disable_pp_tuning = 0;
+       data->registry_data.disable_xlpp_tuning = 0;
+       data->registry_data.disable_workload_policy = 0;
+       data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
+       data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
+       data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
+       data->registry_data.force_workload_policy_mask = 0;
+       data->registry_data.disable_3d_fs_detection = 0;
+       data->registry_data.fps_support = 1;
+       data->registry_data.disable_auto_wattman = 1;
+       data->registry_data.auto_wattman_debug = 0;
+       data->registry_data.auto_wattman_sample_period = 100;
+       data->registry_data.auto_wattman_threshold = 50;
+}
+
+static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       struct amdgpu_device *adev = hwmgr->adev;
+
+       if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE)
+               phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_ControlVDDCI);
+
+       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_TablelessHardwareInterface);
+
+       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_EnableSMU7ThermalManagement);
+
+       if (adev->pg_flags & AMD_PG_SUPPORT_UVD) {
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_UVDPowerGating);
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_UVDDynamicPowerGating);
+       }
+
+       if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_VCEPowerGating);
+
+       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_UnTabledHardwareInterface);
+
+       if (data->registry_data.odn_feature_enable)
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_ODNinACSupport);
+       else {
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_OD6inACSupport);
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_OD6PlusinACSupport);
+       }
+
+       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_ActivityReporting);
+       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_FanSpeedInTableIsRPM);
+
+       if (data->registry_data.od_state_in_dc_support) {
+               if (data->registry_data.odn_feature_enable)
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                                       PHM_PlatformCaps_ODNinDCSupport);
+               else {
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                                       PHM_PlatformCaps_OD6inDCSupport);
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                                       PHM_PlatformCaps_OD6PlusinDCSupport);
+               }
+       }
+
+       if (data->registry_data.thermal_support
+                       && data->registry_data.fuzzy_fan_control_support
+                       && hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_ODFuzzyFanControlSupport);
+
+       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_DynamicPowerManagement);
+       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_SMC);
+       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_ThermalPolicyDelay);
+
+       if (data->registry_data.force_dpm_high)
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
+
+       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_DynamicUVDState);
+
+       if (data->registry_data.sclk_throttle_low_notification)
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_SclkThrottleLowNotification);
+
+       /* power tune caps */
+       /* assume disabled */
+       phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_PowerContainment);
+       phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_DiDtSupport);
+       phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_SQRamping);
+       phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_DBRamping);
+       phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_TDRamping);
+       phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_TCPRamping);
+       phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_DBRRamping);
+       phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_DiDtEDCEnable);
+       phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_GCEDC);
+       phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_PSM);
+
+       if (data->registry_data.didt_support) {
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
+               if (data->registry_data.sq_ramping_support)
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
+               if (data->registry_data.db_ramping_support)
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
+               if (data->registry_data.td_ramping_support)
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
+               if (data->registry_data.tcp_ramping_support)
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
+               if (data->registry_data.dbr_ramping_support)
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
+               if (data->registry_data.edc_didt_support)
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
+               if (data->registry_data.gc_didt_support)
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
+               if (data->registry_data.psm_didt_support)
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
+       }
+
+       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                       PHM_PlatformCaps_RegulatorHot);
+
+       if (data->registry_data.ac_dc_switch_gpio_support) {
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_AutomaticDCTransition);
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
+       }
+
+       if (data->registry_data.quick_transition_support) {
+               phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_AutomaticDCTransition);
+               phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_Falcon_QuickTransition);
+       }
+
+       if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) {
+               phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_LowestUclkReservedForUlv);
+               if (data->lowest_uclk_reserved_for_ulv == 1)
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                                       PHM_PlatformCaps_LowestUclkReservedForUlv);
+       }
+
+       if (data->registry_data.custom_fan_support)
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_CustomFanControlSupport);
+
+       return 0;
+}
+
+static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       int i;
+
+       data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
+                       FEATURE_DPM_PREFETCHER_BIT;
+       data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
+                       FEATURE_DPM_GFXCLK_BIT;
+       data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
+                       FEATURE_DPM_UCLK_BIT;
+       data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
+                       FEATURE_DPM_SOCCLK_BIT;
+       data->smu_features[GNLD_DPM_UVD].smu_feature_id =
+                       FEATURE_DPM_UVD_BIT;
+       data->smu_features[GNLD_DPM_VCE].smu_feature_id =
+                       FEATURE_DPM_VCE_BIT;
+       data->smu_features[GNLD_ULV].smu_feature_id =
+                       FEATURE_ULV_BIT;
+       data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
+                       FEATURE_DPM_MP0CLK_BIT;
+       data->smu_features[GNLD_DPM_LINK].smu_feature_id =
+                       FEATURE_DPM_LINK_BIT;
+       data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
+                       FEATURE_DPM_DCEFCLK_BIT;
+       data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
+                       FEATURE_DS_GFXCLK_BIT;
+       data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
+                       FEATURE_DS_SOCCLK_BIT;
+       data->smu_features[GNLD_DS_LCLK].smu_feature_id =
+                       FEATURE_DS_LCLK_BIT;
+       data->smu_features[GNLD_PPT].smu_feature_id =
+                       FEATURE_PPT_BIT;
+       data->smu_features[GNLD_TDC].smu_feature_id =
+                       FEATURE_TDC_BIT;
+       data->smu_features[GNLD_THERMAL].smu_feature_id =
+                       FEATURE_THERMAL_BIT;
+       data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
+                       FEATURE_GFX_PER_CU_CG_BIT;
+       data->smu_features[GNLD_RM].smu_feature_id =
+                       FEATURE_RM_BIT;
+       data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
+                       FEATURE_DS_DCEFCLK_BIT;
+       data->smu_features[GNLD_ACDC].smu_feature_id =
+                       FEATURE_ACDC_BIT;
+       data->smu_features[GNLD_VR0HOT].smu_feature_id =
+                       FEATURE_VR0HOT_BIT;
+       data->smu_features[GNLD_VR1HOT].smu_feature_id =
+                       FEATURE_VR1HOT_BIT;
+       data->smu_features[GNLD_FW_CTF].smu_feature_id =
+                       FEATURE_FW_CTF_BIT;
+       data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
+                       FEATURE_LED_DISPLAY_BIT;
+       data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
+                       FEATURE_FAN_CONTROL_BIT;
+       data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
+       data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
+       data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
+       data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
+
+       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
+               data->smu_features[i].smu_feature_bitmap =
+                       (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
+               data->smu_features[i].allowed =
+                       ((data->registry_data.disallowed_features >> i) & 1) ?
+                       false : true;
+       }
+}
+
+static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
+{
+       return 0;
+}
+
+static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
+{
+       kfree(hwmgr->backend);
+       hwmgr->backend = NULL;
+
+       return 0;
+}
+
+static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
+{
+       int result = 0;
+       struct vega12_hwmgr *data;
+       struct amdgpu_device *adev = hwmgr->adev;
+
+       data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL);
+       if (data == NULL)
+               return -ENOMEM;
+
+       hwmgr->backend = data;
+
+       vega12_set_default_registry_data(hwmgr);
+
+       data->disable_dpm_mask = 0xff;
+       data->workload_mask = 0xff;
+
+       /* need to set voltage control types before EVV patching */
+       data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE;
+       data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE;
+       data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE;
+
+       data->water_marks_bitmap = 0;
+       data->avfs_exist = false;
+
+       vega12_set_features_platform_caps(hwmgr);
+
+       vega12_init_dpm_defaults(hwmgr);
+
+       /* Parse pptable data read from VBIOS */
+       vega12_set_private_data_based_on_pptable(hwmgr);
+
+       data->is_tlu_enabled = false;
+
+       hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
+                       VEGA12_MAX_HARDWARE_POWERLEVELS;
+       hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
+       hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
+
+       hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
+       /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
+       hwmgr->platform_descriptor.clockStep.engineClock = 500;
+       hwmgr->platform_descriptor.clockStep.memoryClock = 500;
+
+       data->total_active_cus = adev->gfx.cu_info.number;
+       /* Setup default Overdrive Fan control settings */
+       data->odn_fan_table.target_fan_speed =
+                       hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
+       data->odn_fan_table.target_temperature =
+                       hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature;
+       data->odn_fan_table.min_performance_clock =
+                       hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit;
+       data->odn_fan_table.min_fan_limit =
+                       hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit *
+                       hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
+
+       return result;
+}
+
+static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+
+       data->low_sclk_interrupt_threshold = 0;
+
+       return 0;
+}
+
+static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr)
+{
+       PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
+                       "Failed to init sclk threshold!",
+                       return -EINVAL);
+
+       return 0;
+}
+
+/*
+ * @fn vega12_init_dpm_state
+ * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
+ *
+ * @param    dpm_state - the address of the DPM Table to initiailize.
+ * @return   None.
+ */
+static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state)
+{
+       dpm_state->soft_min_level = 0xff;
+       dpm_state->soft_max_level = 0xff;
+       dpm_state->hard_min_level = 0xff;
+       dpm_state->hard_max_level = 0xff;
+}
+
+/*
+ * This function is to initialize all DPM state tables
+ * for SMU based on the dependency table.
+ * Dynamic state patching function will then trim these
+ * state tables to the allowed range based
+ * on the power policy or external client requests,
+ * such as UVD request, etc.
+ */
+static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       struct vega12_single_dpm_table *dpm_table;
+
+       memset(&data->dpm_table, 0, sizeof(data->dpm_table));
+
+       /* Initialize Sclk DPM table based on allow Sclk values */
+       dpm_table = &(data->dpm_table.soc_table);
+       vega12_init_dpm_state(&(dpm_table->dpm_state));
+
+       dpm_table = &(data->dpm_table.gfx_table);
+       vega12_init_dpm_state(&(dpm_table->dpm_state));
+
+       /* Initialize Mclk DPM table based on allow Mclk values */
+       dpm_table = &(data->dpm_table.mem_table);
+       vega12_init_dpm_state(&(dpm_table->dpm_state));
+
+       dpm_table = &(data->dpm_table.eclk_table);
+       vega12_init_dpm_state(&(dpm_table->dpm_state));
+
+       dpm_table = &(data->dpm_table.vclk_table);
+       vega12_init_dpm_state(&(dpm_table->dpm_state));
+
+       dpm_table = &(data->dpm_table.dclk_table);
+       vega12_init_dpm_state(&(dpm_table->dpm_state));
+
+       /* Assume there is no headless Vega12 for now */
+       dpm_table = &(data->dpm_table.dcef_table);
+       vega12_init_dpm_state(&(dpm_table->dpm_state));
+
+       dpm_table = &(data->dpm_table.pixel_table);
+       vega12_init_dpm_state(&(dpm_table->dpm_state));
+
+       dpm_table = &(data->dpm_table.display_table);
+       vega12_init_dpm_state(&(dpm_table->dpm_state));
+
+       dpm_table = &(data->dpm_table.phy_table);
+       vega12_init_dpm_state(&(dpm_table->dpm_state));
+
+       /* save a copy of the default DPM table */
+       memcpy(&(data->golden_dpm_table), &(data->dpm_table),
+                       sizeof(struct vega12_dpm_table));
+
+       return 0;
+}
+
+#if 0
+static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
+       uint32_t min_level;
+
+       hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
+       hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
+
+       /* Optimize compute power profile: Use only highest
+        * 2 power levels (if more than 2 are available)
+        */
+       if (dpm_table->count > 2)
+               min_level = dpm_table->count - 2;
+       else if (dpm_table->count == 2)
+               min_level = 1;
+       else
+               min_level = 0;
+
+       hwmgr->default_compute_power_profile.min_sclk =
+                       dpm_table->dpm_levels[min_level].value;
+
+       hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
+       hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
+
+       return 0;
+}
+#endif
+
+/**
+* Initializes the SMC table and uploads it
+*
+* @param    hwmgr  the address of the powerplay hardware manager.
+* @param    pInput  the pointer to input data (PowerState)
+* @return   always 0
+*/
+static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
+{
+       int result;
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       PPTable_t *pp_table = &(data->smc_state_table.pp_table);
+       struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
+       struct phm_ppt_v3_information *pptable_information =
+               (struct phm_ppt_v3_information *)hwmgr->pptable;
+
+       result = vega12_setup_default_dpm_tables(hwmgr);
+       PP_ASSERT_WITH_CODE(!result,
+                       "Failed to setup default DPM tables!",
+                       return result);
+
+       result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
+       if (!result) {
+               data->vbios_boot_state.vddc     = boot_up_values.usVddc;
+               data->vbios_boot_state.vddci    = boot_up_values.usVddci;
+               data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
+               data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
+               data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
+               data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
+               data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
+               data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
+               if (0 != boot_up_values.usVddc) {
+                       smum_send_msg_to_smc_with_parameter(hwmgr,
+                                               PPSMC_MSG_SetFloorSocVoltage,
+                                               (boot_up_values.usVddc * 4));
+                       data->vbios_boot_state.bsoc_vddc_lock = true;
+               } else {
+                       data->vbios_boot_state.bsoc_vddc_lock = false;
+               }
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                               PPSMC_MSG_SetMinDeepSleepDcefclk,
+                       (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
+       }
+
+       memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
+
+       result = vega12_copy_table_to_smc(hwmgr,
+                       (uint8_t *)pp_table, TABLE_PPTABLE);
+       PP_ASSERT_WITH_CODE(!result,
+                       "Failed to upload PPtable!", return result);
+
+       return 0;
+}
+
+static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       int i;
+       uint32_t allowed_features_low = 0, allowed_features_high = 0;
+
+       for (i = 0; i < GNLD_FEATURES_MAX; i++)
+               if (data->smu_features[i].allowed)
+                       data->smu_features[i].smu_feature_id > 31 ?
+                               (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) :
+                               (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF));
+
+       PP_ASSERT_WITH_CODE(
+               smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high) == 0,
+               "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!",
+               return -1);
+
+       PP_ASSERT_WITH_CODE(
+               smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low) == 0,
+               "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
+               return -1);
+
+       return 0;
+}
+
+static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       uint64_t features_enabled;
+       int i;
+       bool enabled;
+
+       PP_ASSERT_WITH_CODE(
+               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures) == 0,
+               "[EnableAllSMUFeatures] Failed to enable all smu features!",
+               return -1);
+
+       if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
+               for (i = 0; i < GNLD_FEATURES_MAX; i++) {
+                       enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
+                       data->smu_features[i].enabled = enabled;
+                       data->smu_features[i].supported = enabled;
+                       PP_ASSERT(
+                               !data->smu_features[i].allowed || enabled,
+                               "[EnableAllSMUFeatures] Enabled feature is different from allowed, expected disabled!");
+               }
+       }
+
+       return 0;
+}
+
+static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       uint64_t features_enabled;
+       int i;
+       bool enabled;
+
+       PP_ASSERT_WITH_CODE(
+               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures) == 0,
+               "[DisableAllSMUFeatures] Failed to disable all smu features!",
+               return -1);
+
+       if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
+               for (i = 0; i < GNLD_FEATURES_MAX; i++) {
+                       enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
+                       data->smu_features[i].enabled = enabled;
+                       data->smu_features[i].supported = enabled;
+               }
+       }
+
+       return 0;
+}
+
+static int vega12_odn_initialize_default_settings(
+               struct pp_hwmgr *hwmgr)
+{
+       return 0;
+}
+
+static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+{
+       int tmp_result, result = 0;
+
+       smum_send_msg_to_smc_with_parameter(hwmgr,
+                       PPSMC_MSG_NumOfDisplays, 0);
+
+       result = vega12_set_allowed_featuresmask(hwmgr);
+       PP_ASSERT_WITH_CODE(result == 0,
+                       "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
+                       return result);
+
+       tmp_result = vega12_init_smc_table(hwmgr);
+       PP_ASSERT_WITH_CODE(!tmp_result,
+                       "Failed to initialize SMC table!",
+                       result = tmp_result);
+
+       result = vega12_enable_all_smu_features(hwmgr);
+       PP_ASSERT_WITH_CODE(!result,
+                       "Failed to enable all smu features!",
+                       return result);
+
+       tmp_result = vega12_power_control_set_level(hwmgr);
+       PP_ASSERT_WITH_CODE(!tmp_result,
+                       "Failed to power control set level!",
+                       result = tmp_result);
+
+       result = vega12_odn_initialize_default_settings(hwmgr);
+       PP_ASSERT_WITH_CODE(!result,
+                       "Failed to power control set level!",
+                       return result);
+
+       return result;
+}
+
+static int vega12_get_power_state_size(struct pp_hwmgr *hwmgr)
+{
+       return sizeof(struct vega12_power_state);
+}
+
+static int vega12_get_number_of_pp_table_entries(struct pp_hwmgr *hwmgr)
+{
+       return 0;
+}
+
+static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr,
+            struct pp_hw_power_state *hw_ps)
+{
+       return 0;
+}
+
+static int vega12_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+                               struct pp_power_state  *request_ps,
+                       const struct pp_power_state *current_ps)
+{
+       struct vega12_power_state *vega12_ps =
+                               cast_phw_vega12_power_state(&request_ps->hardware);
+       uint32_t sclk;
+       uint32_t mclk;
+       struct PP_Clocks minimum_clocks = {0};
+       bool disable_mclk_switching;
+       bool disable_mclk_switching_for_frame_lock;
+       bool disable_mclk_switching_for_vr;
+       bool force_mclk_high;
+       struct cgs_display_info info = {0};
+       const struct phm_clock_and_voltage_limits *max_limits;
+       uint32_t i;
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       struct phm_ppt_v2_information *table_info =
+                       (struct phm_ppt_v2_information *)(hwmgr->pptable);
+       int32_t count;
+       uint32_t stable_pstate_sclk_dpm_percentage;
+       uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
+       uint32_t latency;
+
+       data->battery_state = (PP_StateUILabel_Battery ==
+                       request_ps->classification.ui_label);
+
+       if (vega12_ps->performance_level_count != 2)
+               pr_info("VI should always have 2 performance levels");
+
+       max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
+                       &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
+                       &(hwmgr->dyn_state.max_clock_voltage_on_dc);
+
+       /* Cap clock DPM tables at DC MAX if it is in DC. */
+       if (PP_PowerSource_DC == hwmgr->power_source) {
+               for (i = 0; i < vega12_ps->performance_level_count; i++) {
+                       if (vega12_ps->performance_levels[i].mem_clock >
+                               max_limits->mclk)
+                               vega12_ps->performance_levels[i].mem_clock =
+                                               max_limits->mclk;
+                       if (vega12_ps->performance_levels[i].gfx_clock >
+                               max_limits->sclk)
+                               vega12_ps->performance_levels[i].gfx_clock =
+                                               max_limits->sclk;
+               }
+       }
+
+       cgs_get_active_displays_info(hwmgr->device, &info);
+
+       /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
+       minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
+       minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
+
+       if (PP_CAP(PHM_PlatformCaps_StablePState)) {
+               PP_ASSERT_WITH_CODE(
+                       data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
+                       data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
+                       "percent sclk value must range from 1% to 100%, setting default value",
+                       stable_pstate_sclk_dpm_percentage = 75);
+
+               max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
+               stable_pstate_sclk = (max_limits->sclk *
+                               stable_pstate_sclk_dpm_percentage) / 100;
+
+               for (count = table_info->vdd_dep_on_sclk->count - 1;
+                               count >= 0; count--) {
+                       if (stable_pstate_sclk >=
+                                       table_info->vdd_dep_on_sclk->entries[count].clk) {
+                               stable_pstate_sclk =
+                                               table_info->vdd_dep_on_sclk->entries[count].clk;
+                               break;
+                       }
+               }
+
+               if (count < 0)
+                       stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
+
+               stable_pstate_mclk = max_limits->mclk;
+
+               minimum_clocks.engineClock = stable_pstate_sclk;
+               minimum_clocks.memoryClock = stable_pstate_mclk;
+       }
+
+       disable_mclk_switching_for_frame_lock = phm_cap_enabled(
+                                   hwmgr->platform_descriptor.platformCaps,
+                                   PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
+       disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
+       force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
+
+       if (info.display_count == 0)
+               disable_mclk_switching = false;
+       else
+               disable_mclk_switching = (info.display_count > 1) ||
+                       disable_mclk_switching_for_frame_lock ||
+                       disable_mclk_switching_for_vr ||
+                       force_mclk_high;
+
+       sclk = vega12_ps->performance_levels[0].gfx_clock;
+       mclk = vega12_ps->performance_levels[0].mem_clock;
+
+       if (sclk < minimum_clocks.engineClock)
+               sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
+                               max_limits->sclk : minimum_clocks.engineClock;
+
+       if (mclk < minimum_clocks.memoryClock)
+               mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
+                               max_limits->mclk : minimum_clocks.memoryClock;
+
+       vega12_ps->performance_levels[0].gfx_clock = sclk;
+       vega12_ps->performance_levels[0].mem_clock = mclk;
+
+       if (vega12_ps->performance_levels[1].gfx_clock <
+                       vega12_ps->performance_levels[0].gfx_clock)
+               vega12_ps->performance_levels[0].gfx_clock =
+                               vega12_ps->performance_levels[1].gfx_clock;
+
+       if (disable_mclk_switching) {
+               /* Set Mclk the max of level 0 and level 1 */
+               if (mclk < vega12_ps->performance_levels[1].mem_clock)
+                       mclk = vega12_ps->performance_levels[1].mem_clock;
+               /* Find the lowest MCLK frequency that is within
+                * the tolerable latency defined in DAL
+                */
+               latency = 0;
+               for (i = 0; i < data->mclk_latency_table.count; i++) {
+                       if ((data->mclk_latency_table.entries[i].latency <= latency) &&
+                               (data->mclk_latency_table.entries[i].frequency >=
+                                               vega12_ps->performance_levels[0].mem_clock) &&
+                               (data->mclk_latency_table.entries[i].frequency <=
+                                               vega12_ps->performance_levels[1].mem_clock))
+                               mclk = data->mclk_latency_table.entries[i].frequency;
+               }
+               vega12_ps->performance_levels[0].mem_clock = mclk;
+       } else {
+               if (vega12_ps->performance_levels[1].mem_clock <
+                               vega12_ps->performance_levels[0].mem_clock)
+                       vega12_ps->performance_levels[0].mem_clock =
+                                       vega12_ps->performance_levels[1].mem_clock;
+       }
+
+       if (PP_CAP(PHM_PlatformCaps_StablePState)) {
+               for (i = 0; i < vega12_ps->performance_level_count; i++) {
+                       vega12_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
+                       vega12_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
+               }
+       }
+
+       return 0;
+}
+
+static int vega12_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       struct PP_Clocks min_clocks = {0};
+       struct cgs_display_info info = {0};
+
+       data->need_update_dpm_table = 0;
+
+       min_clocks.engineClockInSR = hwmgr->display_config.min_core_set_clock_in_sr;
+       if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
+                       (min_clocks.engineClockInSR >= VEGA12_MINIMUM_ENGINE_CLOCK ||
+                        data->display_timing.min_clock_in_sr >= VEGA12_MINIMUM_ENGINE_CLOCK))
+               data->need_update_dpm_table |= DPMTABLE_UPDATE_SCLK;
+
+       cgs_get_active_displays_info(hwmgr->device, &info);
+       if (data->display_timing.num_existing_displays != info.display_count)
+               data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
+
+       return 0;
+}
+
+static int vega12_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
+               struct vega12_single_dpm_table *dpm_table,
+               uint32_t low_limit, uint32_t high_limit)
+{
+       uint32_t i;
+
+       for (i = 0; i < dpm_table->count; i++) {
+               if ((dpm_table->dpm_levels[i].value < low_limit) ||
+                   (dpm_table->dpm_levels[i].value > high_limit))
+                       dpm_table->dpm_levels[i].enabled = false;
+               else
+                       dpm_table->dpm_levels[i].enabled = true;
+       }
+       return 0;
+}
+
+static int vega12_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
+               struct vega12_single_dpm_table *dpm_table,
+               uint32_t low_limit, uint32_t high_limit,
+               uint32_t disable_dpm_mask)
+{
+       uint32_t i;
+
+       for (i = 0; i < dpm_table->count; i++) {
+               if ((dpm_table->dpm_levels[i].value < low_limit) ||
+                   (dpm_table->dpm_levels[i].value > high_limit))
+                       dpm_table->dpm_levels[i].enabled = false;
+               else if ((!((1 << i) & disable_dpm_mask)) &&
+                               !(low_limit == high_limit))
+                       dpm_table->dpm_levels[i].enabled = false;
+               else
+                       dpm_table->dpm_levels[i].enabled = true;
+       }
+       return 0;
+}
+
+static int vega12_trim_dpm_states(struct pp_hwmgr *hwmgr,
+               const struct vega12_power_state *vega12_ps)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       uint32_t high_limit_count;
+
+       PP_ASSERT_WITH_CODE((vega12_ps->performance_level_count >= 1),
+                       "power state did not have any performance level",
+                       return -1);
+
+       high_limit_count = (vega12_ps->performance_level_count == 1) ? 0 : 1;
+
+       vega12_trim_single_dpm_states(hwmgr,
+                       &(data->dpm_table.soc_table),
+                       vega12_ps->performance_levels[0].soc_clock,
+                       vega12_ps->performance_levels[high_limit_count].soc_clock);
+
+       vega12_trim_single_dpm_states_with_mask(hwmgr,
+                       &(data->dpm_table.gfx_table),
+                       vega12_ps->performance_levels[0].gfx_clock,
+                       vega12_ps->performance_levels[high_limit_count].gfx_clock,
+                       data->disable_dpm_mask);
+
+       vega12_trim_single_dpm_states(hwmgr,
+                       &(data->dpm_table.mem_table),
+                       vega12_ps->performance_levels[0].mem_clock,
+                       vega12_ps->performance_levels[high_limit_count].mem_clock);
+
+       return 0;
+}
+
+static uint32_t vega12_find_lowest_dpm_level(
+               struct vega12_single_dpm_table *table)
+{
+       uint32_t i;
+
+       for (i = 0; i < table->count; i++) {
+               if (table->dpm_levels[i].enabled)
+                       break;
+       }
+
+       return i;
+}
+
+static uint32_t vega12_find_highest_dpm_level(
+               struct vega12_single_dpm_table *table)
+{
+       uint32_t i = 0;
+
+       if (table->count <= MAX_REGULAR_DPM_NUMBER) {
+               for (i = table->count; i > 0; i--) {
+                       if (table->dpm_levels[i - 1].enabled)
+                               return i - 1;
+               }
+       } else {
+               pr_info("DPM Table Has Too Many Entries!");
+               return MAX_REGULAR_DPM_NUMBER - 1;
+       }
+
+       return i;
+}
+
+static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
+{
+       return 0;
+}
+
+static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
+{
+       return 0;
+}
+
+static int vega12_generate_dpm_level_enable_mask(
+               struct pp_hwmgr *hwmgr, const void *input)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       const struct phm_set_power_state_input *states =
+                       (const struct phm_set_power_state_input *)input;
+       const struct vega12_power_state *vega12_ps =
+                       cast_const_phw_vega12_power_state(states->pnew_state);
+       int i;
+
+       PP_ASSERT_WITH_CODE(!vega12_trim_dpm_states(hwmgr, vega12_ps),
+                       "Attempt to Trim DPM States Failed!",
+                       return -1);
+
+       data->smc_state_table.gfx_boot_level =
+                       vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
+       data->smc_state_table.gfx_max_level =
+                       vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
+       data->smc_state_table.mem_boot_level =
+                       vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
+       data->smc_state_table.mem_max_level =
+                       vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
+
+       PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
+                       "Attempt to upload DPM Bootup Levels Failed!",
+                       return -1);
+       PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
+                       "Attempt to upload DPM Max Levels Failed!",
+                       return -1);
+       for (i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
+               data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
+
+
+       for (i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
+               data->dpm_table.mem_table.dpm_levels[i].enabled = true;
+
+       return 0;
+}
+
+int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (data->smu_features[GNLD_DPM_VCE].supported) {
+               PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
+                               enable,
+                               data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
+                               "Attempt to Enable/Disable DPM VCE Failed!",
+                               return -1);
+               data->smu_features[GNLD_DPM_VCE].enabled = enable;
+       }
+
+       return 0;
+}
+
+static int vega12_update_sclk_threshold(struct pp_hwmgr *hwmgr)
+{
+       return 0;
+}
+
+static int vega12_set_power_state_tasks(struct pp_hwmgr *hwmgr,
+               const void *input)
+{
+       int tmp_result, result = 0;
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       PPTable_t *pp_table = &(data->smc_state_table.pp_table);
+
+       tmp_result = vega12_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
+       PP_ASSERT_WITH_CODE(!tmp_result,
+                       "Failed to find DPM states clocks in DPM table!",
+                       result = tmp_result);
+
+       tmp_result = vega12_generate_dpm_level_enable_mask(hwmgr, input);
+       PP_ASSERT_WITH_CODE(!tmp_result,
+                       "Failed to generate DPM level enabled mask!",
+                       result = tmp_result);
+
+       tmp_result = vega12_update_sclk_threshold(hwmgr);
+       PP_ASSERT_WITH_CODE(!tmp_result,
+                       "Failed to update SCLK threshold!",
+                       result = tmp_result);
+
+       result = vega12_copy_table_to_smc(hwmgr,
+                       (uint8_t *)pp_table, TABLE_PPTABLE);
+       PP_ASSERT_WITH_CODE(!result,
+                       "Failed to upload PPtable!", return result);
+
+       data->apply_optimized_settings = false;
+       data->apply_overdrive_next_settings_mask = 0;
+
+       return 0;
+}
+
+static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       uint32_t gfx_clk;
+
+       if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
+               return -1;
+
+       if (low)
+               PP_ASSERT_WITH_CODE(
+                       vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
+                       "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
+                       return -1);
+       else
+               PP_ASSERT_WITH_CODE(
+                       vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,
+                       "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
+                       return -1);
+
+       return (gfx_clk * 100);
+}
+
+static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       uint32_t mem_clk;
+
+       if (!data->smu_features[GNLD_DPM_UCLK].enabled)
+               return -1;
+
+       if (low)
+               PP_ASSERT_WITH_CODE(
+                       vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
+                       "[GetMclks]: fail to get min PPCLK_UCLK\n",
+                       return -1);
+       else
+               PP_ASSERT_WITH_CODE(
+                       vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
+                       "[GetMclks]: fail to get max PPCLK_UCLK\n",
+                       return -1);
+
+       return (mem_clk * 100);
+}
+
+static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr,
+               struct pp_gpu_power *query)
+{
+#if 0
+       uint32_t value;
+
+       PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
+                       PPSMC_MSG_GetCurrPkgPwr),
+                       "Failed to get current package power!",
+                       return -EINVAL);
+
+       vega12_read_arg_from_smc(hwmgr, &value);
+       /* power value is an integer */
+       query->average_gpu_power = value << 8;
+#endif
+       return 0;
+}
+
+static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)
+{
+       uint32_t gfx_clk = 0;
+
+       *gfx_freq = 0;
+
+       PP_ASSERT_WITH_CODE(
+                       smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16)) == 0,
+                       "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",
+                       return -1);
+       PP_ASSERT_WITH_CODE(
+                       vega12_read_arg_from_smc(hwmgr, &gfx_clk) == 0,
+                       "[GetCurrentGfxClkFreq] Attempt to read arg from SMC Failed",
+                       return -1);
+
+       *gfx_freq = gfx_clk * 100;
+
+       return 0;
+}
+
+static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)
+{
+       uint32_t mem_clk = 0;
+
+       *mclk_freq = 0;
+
+       PP_ASSERT_WITH_CODE(
+                       smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16)) == 0,
+                       "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",
+                       return -1);
+       PP_ASSERT_WITH_CODE(
+                       vega12_read_arg_from_smc(hwmgr, &mem_clk) == 0,
+                       "[GetCurrentMClkFreq] Attempt to read arg from SMC Failed",
+                       return -1);
+
+       *mclk_freq = mem_clk * 100;
+
+       return 0;
+}
+
+static int vega12_get_current_activity_percent(
+               struct pp_hwmgr *hwmgr,
+               uint32_t *activity_percent)
+{
+       int ret = 0;
+       uint32_t current_activity = 50;
+
+#if 0
+       ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
+       if (!ret) {
+               ret = vega12_read_arg_from_smc(hwmgr, &current_activity);
+               if (!ret) {
+                       if (current_activity > 100) {
+                               PP_ASSERT(false,
+                                       "[GetCurrentActivityPercent] Activity Percentage Exceeds 100!");
+                               current_activity = 100;
+                       }
+               } else
+                       PP_ASSERT(false,
+                               "[GetCurrentActivityPercent] Attempt To Read Average Graphics Activity from SMU Failed!");
+       } else
+               PP_ASSERT(false,
+                       "[GetCurrentActivityPercent] Attempt To Send Get Average Graphics Activity to SMU Failed!");
+#endif
+       *activity_percent = current_activity;
+
+       return ret;
+}
+
+static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx,
+                             void *value, int *size)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       int ret = 0;
+
+       switch (idx) {
+       case AMDGPU_PP_SENSOR_GFX_SCLK:
+               ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);
+               if (!ret)
+                       *size = 4;
+               break;
+       case AMDGPU_PP_SENSOR_GFX_MCLK:
+               ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value);
+               if (!ret)
+                       *size = 4;
+               break;
+       case AMDGPU_PP_SENSOR_GPU_LOAD:
+               ret = vega12_get_current_activity_percent(hwmgr, (uint32_t *)value);
+               if (!ret)
+                       *size = 4;
+               break;
+       case AMDGPU_PP_SENSOR_GPU_TEMP:
+               *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr);
+               *size = 4;
+               break;
+       case AMDGPU_PP_SENSOR_UVD_POWER:
+               *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
+               *size = 4;
+               break;
+       case AMDGPU_PP_SENSOR_VCE_POWER:
+               *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
+               *size = 4;
+               break;
+       case AMDGPU_PP_SENSOR_GPU_POWER:
+               if (*size < sizeof(struct pp_gpu_power))
+                       ret = -EINVAL;
+               else {
+                       *size = sizeof(struct pp_gpu_power);
+                       ret = vega12_get_gpu_power(hwmgr, (struct pp_gpu_power *)value);
+               }
+               break;
+       default:
+               ret = -EINVAL;
+               break;
+       }
+       return ret;
+}
+
+static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
+               bool has_disp)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (data->smu_features[GNLD_DPM_UCLK].enabled)
+               return smum_send_msg_to_smc_with_parameter(hwmgr,
+                       PPSMC_MSG_SetUclkFastSwitch,
+                       has_disp ? 0 : 1);
+
+       return 0;
+}
+
+int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
+               struct pp_display_clock_request *clock_req)
+{
+       int result = 0;
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       enum amd_pp_clock_type clk_type = clock_req->clock_type;
+       uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
+       PPCLK_e clk_select = 0;
+       uint32_t clk_request = 0;
+
+       if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
+               switch (clk_type) {
+               case amd_pp_dcef_clock:
+                       clk_freq = clock_req->clock_freq_in_khz / 100;
+                       clk_select = PPCLK_DCEFCLK;
+                       break;
+               case amd_pp_disp_clock:
+                       clk_select = PPCLK_DISPCLK;
+                       break;
+               case amd_pp_pixel_clock:
+                       clk_select = PPCLK_PIXCLK;
+                       break;
+               case amd_pp_phy_clock:
+                       clk_select = PPCLK_PHYCLK;
+                       break;
+               default:
+                       pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
+                       result = -1;
+                       break;
+               }
+
+               if (!result) {
+                       clk_request = (clk_select << 16) | clk_freq;
+                       result = smum_send_msg_to_smc_with_parameter(hwmgr,
+                                       PPSMC_MSG_SetHardMinByFreq,
+                                       clk_request);
+               }
+       }
+
+       return result;
+}
+
+static int vega12_notify_smc_display_config_after_ps_adjustment(
+               struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       uint32_t num_active_disps = 0;
+       struct cgs_display_info info = {0};
+       struct PP_Clocks min_clocks = {0};
+       struct pp_display_clock_request clock_req;
+       uint32_t clk_request;
+
+       info.mode_info = NULL;
+       cgs_get_active_displays_info(hwmgr->device, &info);
+       num_active_disps = info.display_count;
+       if (num_active_disps > 1)
+               vega12_notify_smc_display_change(hwmgr, false);
+       else
+               vega12_notify_smc_display_change(hwmgr, true);
+
+       min_clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
+       min_clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk;
+       min_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
+
+       if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
+               clock_req.clock_type = amd_pp_dcef_clock;
+               clock_req.clock_freq_in_khz = min_clocks.dcefClock;
+               if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) {
+                       if (data->smu_features[GNLD_DS_DCEFCLK].supported)
+                               PP_ASSERT_WITH_CODE(
+                                       !smum_send_msg_to_smc_with_parameter(
+                                       hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
+                                       min_clocks.dcefClockInSR /100),
+                                       "Attempt to set divider for DCEFCLK Failed!",
+                                       return -1);
+               } else {
+                       pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
+               }
+       }
+
+       if (data->smu_features[GNLD_DPM_UCLK].enabled) {
+               clk_request = (PPCLK_UCLK << 16) | (min_clocks.memoryClock) / 100;
+               PP_ASSERT_WITH_CODE(
+                       smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetHardMinByFreq, clk_request) == 0,
+                       "[PhwVega12_NotifySMCDisplayConfigAfterPowerStateAdjustment] Attempt to set UCLK HardMin Failed!",
+                       return -1);
+               data->dpm_table.mem_table.dpm_state.hard_min_level = min_clocks.memoryClock;
+       }
+
+       return 0;
+}
+
+static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+
+       data->smc_state_table.gfx_boot_level =
+       data->smc_state_table.gfx_max_level =
+                       vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
+       data->smc_state_table.mem_boot_level =
+       data->smc_state_table.mem_max_level =
+                       vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
+
+       PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
+                       "Failed to upload boot level to highest!",
+                       return -1);
+
+       PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
+                       "Failed to upload dpm max level to highest!",
+                       return -1);
+
+       return 0;
+}
+
+static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+
+       data->smc_state_table.gfx_boot_level =
+       data->smc_state_table.gfx_max_level =
+                       vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
+       data->smc_state_table.mem_boot_level =
+       data->smc_state_table.mem_max_level =
+                       vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
+
+       PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
+                       "Failed to upload boot level to highest!",
+                       return -1);
+
+       PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
+                       "Failed to upload dpm max level to highest!",
+                       return -1);
+
+       return 0;
+
+}
+
+static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       data->smc_state_table.gfx_boot_level =
+                       vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
+       data->smc_state_table.gfx_max_level =
+                       vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
+       data->smc_state_table.mem_boot_level =
+                       vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
+       data->smc_state_table.mem_max_level =
+                       vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
+
+       PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
+                       "Failed to upload DPM Bootup Levels!",
+                       return -1);
+
+       PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
+                       "Failed to upload DPM Max Levels!",
+                       return -1);
+       return 0;
+}
+
+#if 0
+static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
+                               uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
+{
+       struct phm_ppt_v2_information *table_info =
+                       (struct phm_ppt_v2_information *)(hwmgr->pptable);
+
+       if (table_info->vdd_dep_on_sclk->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
+               table_info->vdd_dep_on_socclk->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL &&
+               table_info->vdd_dep_on_mclk->count > VEGA12_UMD_PSTATE_MCLK_LEVEL) {
+               *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL;
+               *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
+               *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
+       }
+
+       if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
+               *sclk_mask = 0;
+       } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
+               *mclk_mask = 0;
+       } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+               *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
+               *soc_mask = table_info->vdd_dep_on_socclk->count - 1;
+               *mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
+       }
+       return 0;
+}
+#endif
+
+static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
+{
+       switch (mode) {
+       case AMD_FAN_CTRL_NONE:
+               break;
+       case AMD_FAN_CTRL_MANUAL:
+               if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
+                       vega12_fan_ctrl_stop_smc_fan_control(hwmgr);
+               break;
+       case AMD_FAN_CTRL_AUTO:
+               if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
+                       vega12_fan_ctrl_start_smc_fan_control(hwmgr);
+               break;
+       default:
+               break;
+       }
+}
+
+static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
+                               enum amd_dpm_forced_level level)
+{
+       int ret = 0;
+#if 0
+       uint32_t sclk_mask = 0;
+       uint32_t mclk_mask = 0;
+       uint32_t soc_mask = 0;
+#endif
+
+       switch (level) {
+       case AMD_DPM_FORCED_LEVEL_HIGH:
+               ret = vega12_force_dpm_highest(hwmgr);
+               break;
+       case AMD_DPM_FORCED_LEVEL_LOW:
+               ret = vega12_force_dpm_lowest(hwmgr);
+               break;
+       case AMD_DPM_FORCED_LEVEL_AUTO:
+               ret = vega12_unforce_dpm_levels(hwmgr);
+               break;
+       case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+       case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+       case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+       case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+#if 0
+               ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
+               if (ret)
+                       return ret;
+               vega12_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
+               vega12_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
+#endif
+               break;
+       case AMD_DPM_FORCED_LEVEL_MANUAL:
+       case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+       default:
+               break;
+       }
+#if 0
+       if (!ret) {
+               if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+                       vega12_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
+               else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+                       vega12_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
+       }
+#endif
+       return ret;
+}
+
+static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
+               return AMD_FAN_CTRL_MANUAL;
+       else
+               return AMD_FAN_CTRL_AUTO;
+}
+
+static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
+               struct amd_pp_simple_clock_info *info)
+{
+#if 0
+       struct phm_ppt_v2_information *table_info =
+                       (struct phm_ppt_v2_information *)hwmgr->pptable;
+       struct phm_clock_and_voltage_limits *max_limits =
+                       &table_info->max_clock_voltage_on_ac;
+
+       info->engine_max_clock = max_limits->sclk;
+       info->memory_max_clock = max_limits->mclk;
+#endif
+       return 0;
+}
+
+static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
+               uint32_t *clock,
+               PPCLK_e clock_select,
+               bool max)
+{
+       int result;
+       *clock = 0;
+
+       if (max) {
+                PP_ASSERT_WITH_CODE(
+                       smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16)) == 0,
+                       "[GetClockRanges] Failed to get max clock from SMC!",
+                       return -1);
+               result = vega12_read_arg_from_smc(hwmgr, clock);
+       } else {
+               PP_ASSERT_WITH_CODE(
+                       smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clock_select << 16)) == 0,
+                       "[GetClockRanges] Failed to get min clock from SMC!",
+                       return -1);
+               result = vega12_read_arg_from_smc(hwmgr, clock);
+       }
+
+       return result;
+}
+
+static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
+               struct pp_clock_levels_with_latency *clocks)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       int i;
+       uint32_t min, max, increments;
+
+       if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
+               return -1;
+
+       PP_ASSERT_WITH_CODE(
+               vega12_get_clock_ranges(hwmgr, &min, PPCLK_GFXCLK, false) == 0,
+               "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
+               return -1);
+       PP_ASSERT_WITH_CODE(
+               vega12_get_clock_ranges(hwmgr, &max, PPCLK_GFXCLK, true) == 0,
+               "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
+               return -1);
+
+       clocks->data[0].clocks_in_khz = min * 100;
+       increments = (max - min) / (VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS - 1);
+
+       for (i = 1; i < (VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS - 1); i++) {
+               if ((min + (increments * i)) != 0) {
+                       clocks->data[i].clocks_in_khz =
+                               (min + increments * i) * 100;
+                       clocks->data[i].latency_in_us = 0;
+               }
+       }
+       clocks->data[i].clocks_in_khz = max * 100;
+       clocks->num_levels = i + 1;
+
+       return 0;
+}
+
+static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr,
+               uint32_t clock)
+{
+       return 25;
+}
+
+static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
+               struct pp_clock_levels_with_latency *clocks)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       uint32_t min, max, increments;
+       int i;
+
+       if (!data->smu_features[GNLD_DPM_UCLK].enabled)
+               return -1;
+
+       PP_ASSERT_WITH_CODE(
+               vega12_get_clock_ranges(hwmgr, &min, PPCLK_UCLK, false) == 0,
+               "[GetMclks]: fail to get min PPCLK_UCLK\n",
+               return -1);
+       PP_ASSERT_WITH_CODE(
+               vega12_get_clock_ranges(hwmgr, &max, PPCLK_UCLK, true) == 0,
+               "[GetMclks]: fail to get max PPCLK_UCLK\n",
+               return -1);
+
+       clocks->data[0].clocks_in_khz = min * 100;
+       clocks->data[0].latency_in_us =
+               data->mclk_latency_table.entries[0].latency =
+               vega12_get_mem_latency(hwmgr, min);
+
+       increments = (max - min) / (VG12_PSUEDO_NUM_UCLK_DPM_LEVELS - 1);
+
+       for (i = 1; i < (VG12_PSUEDO_NUM_UCLK_DPM_LEVELS - 1); i++) {
+               if ((min + (increments * i)) != 0) {
+                       clocks->data[i].clocks_in_khz =
+                               (min + (increments * i)) * 100;
+                       clocks->data[i].latency_in_us =
+                               data->mclk_latency_table.entries[i].latency =
+                               vega12_get_mem_latency(hwmgr, min + increments * i);
+               }
+       }
+
+       clocks->data[i].clocks_in_khz = max * 100;
+       clocks->data[i].latency_in_us =
+               data->mclk_latency_table.entries[i].latency =
+               vega12_get_mem_latency(hwmgr, max);
+
+       clocks->num_levels = data->mclk_latency_table.count = i + 1;
+
+       return 0;
+}
+
+static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
+               struct pp_clock_levels_with_latency *clocks)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       int i;
+       uint32_t min, max, increments;
+
+       if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
+               return -1;
+
+       PP_ASSERT_WITH_CODE(
+               vega12_get_clock_ranges(hwmgr, &min, PPCLK_DCEFCLK, false) == 0,
+               "[GetDcfclocks]: fail to get min PPCLK_DCEFCLK\n",
+               return -1);
+       PP_ASSERT_WITH_CODE(
+               vega12_get_clock_ranges(hwmgr, &max, PPCLK_DCEFCLK, true) == 0,
+               "[GetDcfclocks]: fail to get max PPCLK_DCEFCLK\n",
+               return -1);
+
+       clocks->data[0].clocks_in_khz = min * 100;
+       increments = (max - min) / (VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS - 1);
+
+       for (i = 1; i < (VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS - 1); i++) {
+               if ((min + (increments * i)) != 0) {
+                       clocks->data[i].clocks_in_khz =
+                               (min + increments * i) * 100;
+                       clocks->data[i].latency_in_us = 0;
+               }
+       }
+       clocks->data[i].clocks_in_khz = max * 100;
+       clocks->num_levels = i + 1;
+
+       return 0;
+}
+
+static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
+               struct pp_clock_levels_with_latency *clocks)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       int i;
+       uint32_t min, max, increments;
+
+       if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
+               return -1;
+
+       PP_ASSERT_WITH_CODE(
+               vega12_get_clock_ranges(hwmgr, &min, PPCLK_SOCCLK, false) == 0,
+               "[GetSocclks]: fail to get min PPCLK_SOCCLK\n",
+               return -1);
+       PP_ASSERT_WITH_CODE(
+               vega12_get_clock_ranges(hwmgr, &max, PPCLK_SOCCLK, true) == 0,
+               "[GetSocclks]: fail to get max PPCLK_SOCCLK\n",
+               return -1);
+
+       clocks->data[0].clocks_in_khz = min * 100;
+       increments = (max - min) / (VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS - 1);
+
+       for (i = 1; i < (VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS - 1); i++) {
+               if ((min + (increments * i)) != 0) {
+                       clocks->data[i].clocks_in_khz =
+                               (min + increments * i) * 100;
+                       clocks->data[i].latency_in_us = 0;
+               }
+       }
+
+       clocks->data[i].clocks_in_khz = max * 100;
+       clocks->num_levels = i + 1;
+
+       return 0;
+
+}
+
+static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
+               enum amd_pp_clock_type type,
+               struct pp_clock_levels_with_latency *clocks)
+{
+       int ret;
+
+       switch (type) {
+       case amd_pp_sys_clock:
+               ret = vega12_get_sclks(hwmgr, clocks);
+               break;
+       case amd_pp_mem_clock:
+               ret = vega12_get_memclocks(hwmgr, clocks);
+               break;
+       case amd_pp_dcef_clock:
+               ret = vega12_get_dcefclocks(hwmgr, clocks);
+               break;
+       case amd_pp_soc_clock:
+               ret = vega12_get_socclocks(hwmgr, clocks);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       return ret;
+}
+
+static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
+               enum amd_pp_clock_type type,
+               struct pp_clock_levels_with_voltage *clocks)
+{
+       clocks->num_levels = 0;
+
+       return 0;
+}
+
+static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+               struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       Watermarks_t *table = &(data->smc_state_table.water_marks_table);
+       int result = 0;
+       uint32_t i;
+
+       if (!data->registry_data.disable_water_mark &&
+                       data->smu_features[GNLD_DPM_DCEFCLK].supported &&
+                       data->smu_features[GNLD_DPM_SOCCLK].supported) {
+               for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
+                       table->WatermarkRow[WM_DCEFCLK][i].MinClock =
+                               cpu_to_le16((uint16_t)
+                               (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
+                               100);
+                       table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
+                               cpu_to_le16((uint16_t)
+                               (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
+                               100);
+                       table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
+                               cpu_to_le16((uint16_t)
+                               (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_memclk_in_khz) /
+                               100);
+                       table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
+                               cpu_to_le16((uint16_t)
+                               (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_memclk_in_khz) /
+                               100);
+                       table->WatermarkRow[WM_DCEFCLK][i].WmSetting = (uint8_t)
+                                       wm_with_clock_ranges->wm_sets_dmif[i].wm_set_id;
+               }
+
+               for (i = 0; i < wm_with_clock_ranges->num_wm_sets_mcif; i++) {
+                       table->WatermarkRow[WM_SOCCLK][i].MinClock =
+                               cpu_to_le16((uint16_t)
+                               (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_socclk_in_khz) /
+                               100);
+                       table->WatermarkRow[WM_SOCCLK][i].MaxClock =
+                               cpu_to_le16((uint16_t)
+                               (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_socclk_in_khz) /
+                               100);
+                       table->WatermarkRow[WM_SOCCLK][i].MinUclk =
+                               cpu_to_le16((uint16_t)
+                               (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_memclk_in_khz) /
+                               100);
+                       table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
+                               cpu_to_le16((uint16_t)
+                               (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_memclk_in_khz) /
+                               100);
+                       table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
+                                       wm_with_clock_ranges->wm_sets_mcif[i].wm_set_id;
+               }
+               data->water_marks_bitmap |= WaterMarksExist;
+               data->water_marks_bitmap &= ~WaterMarksLoaded;
+       }
+
+       return result;
+}
+
+static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
+               enum pp_clock_type type, uint32_t mask)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
+                               AMD_DPM_FORCED_LEVEL_LOW |
+                               AMD_DPM_FORCED_LEVEL_HIGH))
+               return -EINVAL;
+
+       switch (type) {
+       case PP_SCLK:
+               data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
+               data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
+
+               PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
+                       "Failed to upload boot level to lowest!",
+                       return -EINVAL);
+
+               PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
+                       "Failed to upload dpm max level to highest!",
+                       return -EINVAL);
+               break;
+
+       case PP_MCLK:
+               data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
+               data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
+
+               PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
+                       "Failed to upload boot level to lowest!",
+                       return -EINVAL);
+
+               PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
+                       "Failed to upload dpm max level to highest!",
+                       return -EINVAL);
+
+               break;
+
+       case PP_PCIE:
+               break;
+
+       default:
+               break;
+       }
+
+       return 0;
+}
+
+static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
+               enum pp_clock_type type, char *buf)
+{
+       int i, now, size = 0;
+       struct pp_clock_levels_with_latency clocks;
+
+       switch (type) {
+       case PP_SCLK:
+               PP_ASSERT_WITH_CODE(
+                               vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0,
+                               "Attempt to get current gfx clk Failed!",
+                               return -1);
+
+               PP_ASSERT_WITH_CODE(
+                               vega12_get_sclks(hwmgr, &clocks) == 0,
+                               "Attempt to get gfx clk levels Failed!",
+                               return -1);
+               for (i = 0; i < clocks.num_levels; i++)
+                       size += sprintf(buf + size, "%d: %uMhz %s\n",
+                               i, clocks.data[i].clocks_in_khz / 100,
+                               (clocks.data[i].clocks_in_khz == now) ? "*" : "");
+               break;
+
+       case PP_MCLK:
+               PP_ASSERT_WITH_CODE(
+                               vega12_get_current_mclk_freq(hwmgr, &now) == 0,
+                               "Attempt to get current mclk freq Failed!",
+                               return -1);
+
+               PP_ASSERT_WITH_CODE(
+                               vega12_get_memclocks(hwmgr, &clocks) == 0,
+                               "Attempt to get memory clk levels Failed!",
+                               return -1);
+               for (i = 0; i < clocks.num_levels; i++)
+                       size += sprintf(buf + size, "%d: %uMhz %s\n",
+                               i, clocks.data[i].clocks_in_khz / 100,
+                               (clocks.data[i].clocks_in_khz == now) ? "*" : "");
+               break;
+
+       case PP_PCIE:
+               break;
+
+       default:
+               break;
+       }
+       return size;
+}
+
+static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       int result = 0;
+       uint32_t num_turned_on_displays = 1;
+       Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
+       struct cgs_display_info info = {0};
+
+       if ((data->water_marks_bitmap & WaterMarksExist) &&
+                       !(data->water_marks_bitmap & WaterMarksLoaded)) {
+               result = vega12_copy_table_to_smc(hwmgr,
+                       (uint8_t *)wm_table, TABLE_WATERMARKS);
+               PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
+               data->water_marks_bitmap |= WaterMarksLoaded;
+       }
+
+       if ((data->water_marks_bitmap & WaterMarksExist) &&
+               data->smu_features[GNLD_DPM_DCEFCLK].supported &&
+               data->smu_features[GNLD_DPM_SOCCLK].supported) {
+               cgs_get_active_displays_info(hwmgr->device, &info);
+               num_turned_on_displays = info.display_count;
+               smum_send_msg_to_smc_with_parameter(hwmgr,
+                       PPSMC_MSG_NumOfDisplays, num_turned_on_displays);
+       }
+
+       return result;
+}
+
+int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (data->smu_features[GNLD_DPM_UVD].supported) {
+               PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
+                               enable,
+                               data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
+                               "Attempt to Enable/Disable DPM UVD Failed!",
+                               return -1);
+               data->smu_features[GNLD_DPM_UVD].enabled = enable;
+       }
+
+       return 0;
+}
+
+static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       data->vce_power_gated = bgate;
+       vega12_enable_disable_vce_dpm(hwmgr, !bgate);
+}
+
+static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       data->uvd_power_gated = bgate;
+       vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
+}
+
+static inline bool vega12_are_power_levels_equal(
+                               const struct vega12_performance_level *pl1,
+                               const struct vega12_performance_level *pl2)
+{
+       return ((pl1->soc_clock == pl2->soc_clock) &&
+                       (pl1->gfx_clock == pl2->gfx_clock) &&
+                       (pl1->mem_clock == pl2->mem_clock));
+}
+
+static int vega12_check_states_equal(struct pp_hwmgr *hwmgr,
+                               const struct pp_hw_power_state *pstate1,
+                       const struct pp_hw_power_state *pstate2, bool *equal)
+{
+       const struct vega12_power_state *psa;
+       const struct vega12_power_state *psb;
+       int i;
+
+       if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
+               return -EINVAL;
+
+       psa = cast_const_phw_vega12_power_state(pstate1);
+       psb = cast_const_phw_vega12_power_state(pstate2);
+       /* If the two states don't even have the same number of performance levels they cannot be the same state. */
+       if (psa->performance_level_count != psb->performance_level_count) {
+               *equal = false;
+               return 0;
+       }
+
+       for (i = 0; i < psa->performance_level_count; i++) {
+               if (!vega12_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
+                       /* If we have found even one performance level pair that is different the states are different. */
+                       *equal = false;
+                       return 0;
+               }
+       }
+
+       /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
+       *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
+       *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
+       *equal &= (psa->sclk_threshold == psb->sclk_threshold);
+
+       return 0;
+}
+
+static bool
+vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       bool is_update_required = false;
+       struct cgs_display_info info = {0, 0, NULL};
+
+       cgs_get_active_displays_info(hwmgr->device, &info);
+
+       if (data->display_timing.num_existing_displays != info.display_count)
+               is_update_required = true;
+
+       if (data->registry_data.gfx_clk_deep_sleep_support) {
+               if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr)
+                       is_update_required = true;
+       }
+
+       return is_update_required;
+}
+
+static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
+{
+       int tmp_result, result = 0;
+
+       tmp_result = vega12_disable_all_smu_features(hwmgr);
+       PP_ASSERT_WITH_CODE((tmp_result == 0),
+                       "Failed to disable all smu features!", result = tmp_result);
+
+       return result;
+}
+
+static int vega12_power_off_asic(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       int result;
+
+       result = vega12_disable_dpm_tasks(hwmgr);
+       PP_ASSERT_WITH_CODE((0 == result),
+                       "[disable_dpm_tasks] Failed to disable DPM!",
+                       );
+       data->water_marks_bitmap &= ~(WaterMarksLoaded);
+
+       return result;
+}
+
+#if 0
+static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
+               uint32_t *sclk_idx, uint32_t *mclk_idx,
+               uint32_t min_sclk, uint32_t min_mclk)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       struct vega12_dpm_table *dpm_table = &(data->dpm_table);
+       uint32_t i;
+
+       for (i = 0; i < dpm_table->gfx_table.count; i++) {
+               if (dpm_table->gfx_table.dpm_levels[i].enabled &&
+                       dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
+                       *sclk_idx = i;
+                       break;
+               }
+       }
+
+       for (i = 0; i < dpm_table->mem_table.count; i++) {
+               if (dpm_table->mem_table.dpm_levels[i].enabled &&
+                       dpm_table->mem_table.dpm_levels[i].value >= min_mclk) {
+                       *mclk_idx = i;
+                       break;
+               }
+       }
+}
+#endif
+
+#if 0
+static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
+               struct amd_pp_profile *request)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       uint32_t sclk_idx = ~0, mclk_idx = ~0;
+
+       if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
+               return -EINVAL;
+
+       vega12_find_min_clock_index(hwmgr, &sclk_idx, &mclk_idx,
+                       request->min_sclk, request->min_mclk);
+
+       if (sclk_idx != ~0) {
+               if (!data->registry_data.sclk_dpm_key_disabled)
+                       PP_ASSERT_WITH_CODE(
+                                       !smum_send_msg_to_smc_with_parameter(
+                                       hwmgr,
+                                       PPSMC_MSG_SetSoftMinGfxclkByIndex,
+                                       sclk_idx),
+                                       "Failed to set soft min sclk index!",
+                                       return -EINVAL);
+       }
+
+       if (mclk_idx != ~0) {
+               if (!data->registry_data.mclk_dpm_key_disabled)
+                       PP_ASSERT_WITH_CODE(
+                                       !smum_send_msg_to_smc_with_parameter(
+                                       hwmgr,
+                                       PPSMC_MSG_SetSoftMinUclkByIndex,
+                                       mclk_idx),
+                                       "Failed to set soft min mclk index!",
+                                       return -EINVAL);
+       }
+
+       return 0;
+}
+
+static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
+       struct vega12_single_dpm_table *golden_sclk_table =
+                       &(data->golden_dpm_table.gfx_table);
+       int value;
+
+       value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
+                       golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
+                       100 /
+                       golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
+
+       return value;
+}
+
+static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       struct vega12_single_dpm_table *golden_sclk_table =
+                       &(data->golden_dpm_table.gfx_table);
+       struct pp_power_state *ps;
+       struct vega12_power_state *vega12_ps;
+
+       ps = hwmgr->request_ps;
+
+       if (ps == NULL)
+               return -EINVAL;
+
+       vega12_ps = cast_phw_vega12_power_state(&ps->hardware);
+
+       vega12_ps->performance_levels[vega12_ps->performance_level_count - 1].gfx_clock =
+               golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value / 100 +
+               golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
+
+       if (vega12_ps->performance_levels[vega12_ps->performance_level_count - 1].gfx_clock >
+                       hwmgr->platform_descriptor.overdriveLimit.engineClock)
+               vega12_ps->performance_levels[vega12_ps->performance_level_count - 1].gfx_clock =
+                       hwmgr->platform_descriptor.overdriveLimit.engineClock;
+
+       return 0;
+}
+
+static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
+       struct vega12_single_dpm_table *golden_mclk_table =
+                       &(data->golden_dpm_table.mem_table);
+       int value;
+
+       value = (mclk_table->dpm_levels
+                       [mclk_table->count - 1].value -
+                       golden_mclk_table->dpm_levels
+                       [golden_mclk_table->count - 1].value) *
+                       100 /
+                       golden_mclk_table->dpm_levels
+                       [golden_mclk_table->count - 1].value;
+
+       return value;
+}
+
+static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       struct vega12_single_dpm_table *golden_mclk_table =
+                       &(data->golden_dpm_table.mem_table);
+       struct pp_power_state  *ps;
+       struct vega12_power_state  *vega12_ps;
+
+       ps = hwmgr->request_ps;
+
+       if (ps == NULL)
+               return -EINVAL;
+
+       vega12_ps = cast_phw_vega12_power_state(&ps->hardware);
+
+       vega12_ps->performance_levels
+       [vega12_ps->performance_level_count - 1].mem_clock =
+                       golden_mclk_table->dpm_levels
+                       [golden_mclk_table->count - 1].value *
+                       value / 100 +
+                       golden_mclk_table->dpm_levels
+                       [golden_mclk_table->count - 1].value;
+
+       if (vega12_ps->performance_levels
+                       [vega12_ps->performance_level_count - 1].mem_clock >
+                       hwmgr->platform_descriptor.overdriveLimit.memoryClock)
+               vega12_ps->performance_levels
+               [vega12_ps->performance_level_count - 1].mem_clock =
+                               hwmgr->platform_descriptor.overdriveLimit.memoryClock;
+
+       return 0;
+}
+#endif
+
+static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
+                                       uint32_t virtual_addr_low,
+                                       uint32_t virtual_addr_hi,
+                                       uint32_t mc_addr_low,
+                                       uint32_t mc_addr_hi,
+                                       uint32_t size)
+{
+       smum_send_msg_to_smc_with_parameter(hwmgr,
+                                       PPSMC_MSG_SetSystemVirtualDramAddrHigh,
+                                       virtual_addr_hi);
+       smum_send_msg_to_smc_with_parameter(hwmgr,
+                                       PPSMC_MSG_SetSystemVirtualDramAddrLow,
+                                       virtual_addr_low);
+       smum_send_msg_to_smc_with_parameter(hwmgr,
+                                       PPSMC_MSG_DramLogSetDramAddrHigh,
+                                       mc_addr_hi);
+
+       smum_send_msg_to_smc_with_parameter(hwmgr,
+                                       PPSMC_MSG_DramLogSetDramAddrLow,
+                                       mc_addr_low);
+
+       smum_send_msg_to_smc_with_parameter(hwmgr,
+                                       PPSMC_MSG_DramLogSetDramSize,
+                                       size);
+       return 0;
+}
+
+static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
+               struct PP_TemperatureRange *thermal_data)
+{
+       struct phm_ppt_v3_information *pptable_information =
+               (struct phm_ppt_v3_information *)hwmgr->pptable;
+
+       memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
+
+       thermal_data->max = pptable_information->us_software_shutdown_temp *
+               PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+       return 0;
+}
+
+static int vega12_is_hardware_ctf_enabled(struct pp_hwmgr *hwmgr)
+{
+       uint32_t reg;
+
+       reg = soc15_get_register_offset(THM_HWID, 0,
+                       mmTHM_TCON_THERM_TRIP_BASE_IDX,
+                       mmTHM_TCON_THERM_TRIP);
+
+       return (((cgs_read_register(hwmgr->device, reg) &
+               THM_TCON_THERM_TRIP__THERM_TP_EN_MASK) >>
+               THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT) == 1);
+}
+
+static int vega12_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
+               const void *info)
+{
+       struct cgs_irq_src_funcs *irq_src =
+                       (struct cgs_irq_src_funcs *)info;
+
+       if (hwmgr->thermal_controller.ucType ==
+                       ATOM_VEGA12_PP_THERMALCONTROLLER_VEGA12) {
+               PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
+                               0xf, /* AMDGPU_IH_CLIENTID_THM */
+                               0, 0, irq_src[0].set, irq_src[0].handler, hwmgr),
+                               "Failed to register high thermal interrupt!",
+                               return -EINVAL);
+               PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
+                               0xf, /* AMDGPU_IH_CLIENTID_THM */
+                               1, 0, irq_src[1].set, irq_src[1].handler, hwmgr),
+                               "Failed to register low thermal interrupt!",
+                               return -EINVAL);
+       }
+
+       if (vega12_is_hardware_ctf_enabled(hwmgr))
+               /* Register CTF(GPIO_19) interrupt */
+               PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
+                               0x16, /* AMDGPU_IH_CLIENTID_ROM_SMUIO, */
+                               83, 0, irq_src[2].set, irq_src[2].handler, hwmgr),
+                               "Failed to register CTF thermal interrupt!",
+                               return -EINVAL);
+
+       return 0;
+}
+
+static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
+       .backend_init = vega12_hwmgr_backend_init,
+       .backend_fini = vega12_hwmgr_backend_fini,
+       .asic_setup = vega12_setup_asic_task,
+       .dynamic_state_management_enable = vega12_enable_dpm_tasks,
+       .dynamic_state_management_disable = vega12_disable_dpm_tasks,
+       .get_num_of_pp_table_entries =
+                       vega12_get_number_of_pp_table_entries,
+       .get_power_state_size = vega12_get_power_state_size,
+       .patch_boot_state = vega12_patch_boot_state,
+       .apply_state_adjust_rules = vega12_apply_state_adjust_rules,
+       .power_state_set = vega12_set_power_state_tasks,
+       .get_sclk = vega12_dpm_get_sclk,
+       .get_mclk = vega12_dpm_get_mclk,
+       .notify_smc_display_config_after_ps_adjustment =
+                       vega12_notify_smc_display_config_after_ps_adjustment,
+       .force_dpm_level = vega12_dpm_force_dpm_level,
+       .stop_thermal_controller = vega12_thermal_stop_thermal_controller,
+       .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info,
+       .reset_fan_speed_to_default =
+                       vega12_fan_ctrl_reset_fan_speed_to_default,
+       .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm,
+       .set_fan_control_mode = vega12_set_fan_control_mode,
+       .get_fan_control_mode = vega12_get_fan_control_mode,
+       .read_sensor = vega12_read_sensor,
+       .get_dal_power_level = vega12_get_dal_power_level,
+       .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency,
+       .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage,
+       .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
+       .display_clock_voltage_request = vega12_display_clock_voltage_request,
+       .force_clock_level = vega12_force_clock_level,
+       .print_clock_levels = vega12_print_clock_levels,
+       .display_config_changed = vega12_display_configuration_changed_task,
+       .powergate_uvd = vega12_power_gate_uvd,
+       .powergate_vce = vega12_power_gate_vce,
+       .check_states_equal = vega12_check_states_equal,
+       .check_smc_update_required_for_display_configuration =
+                       vega12_check_smc_update_required_for_display_configuration,
+       .power_off_asic = vega12_power_off_asic,
+       .disable_smc_firmware_ctf = vega12_thermal_disable_alert,
+#if 0
+       .set_power_profile_state = vega12_set_power_profile_state,
+       .get_sclk_od = vega12_get_sclk_od,
+       .set_sclk_od = vega12_set_sclk_od,
+       .get_mclk_od = vega12_get_mclk_od,
+       .set_mclk_od = vega12_set_mclk_od,
+#endif
+       .notify_cac_buffer_info = vega12_notify_cac_buffer_info,
+       .get_thermal_temperature_range = vega12_get_thermal_temperature_range,
+       .register_internal_thermal_interrupt = vega12_register_thermal_interrupt,
+       .start_thermal_controller = vega12_start_thermal_controller,
+};
+
+int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
+{
+       hwmgr->hwmgr_func = &vega12_hwmgr_funcs;
+       hwmgr->pptable_func = &vega12_pptable_funcs;
+
+       return 0;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
new file mode 100644 (file)
index 0000000..80791d6
--- /dev/null
@@ -0,0 +1,470 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _VEGA12_HWMGR_H_
+#define _VEGA12_HWMGR_H_
+
+#include "hwmgr.h"
+#include "vega12/smu9_driver_if.h"
+#include "ppatomfwctrl.h"
+
+#define VEGA12_MAX_HARDWARE_POWERLEVELS 2
+
+#define WaterMarksExist  1
+#define WaterMarksLoaded 2
+
+#define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS   8
+#define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS   8
+#define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS  8
+#define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS     4
+
+enum
+{
+       GNLD_DPM_PREFETCHER = 0,
+       GNLD_DPM_GFXCLK,
+       GNLD_DPM_UCLK,
+       GNLD_DPM_SOCCLK,
+       GNLD_DPM_UVD,
+       GNLD_DPM_VCE,
+       GNLD_ULV,
+       GNLD_DPM_MP0CLK,
+       GNLD_DPM_LINK,
+       GNLD_DPM_DCEFCLK,
+       GNLD_DS_GFXCLK,
+       GNLD_DS_SOCCLK,
+       GNLD_DS_LCLK,
+       GNLD_PPT,
+       GNLD_TDC,
+       GNLD_THERMAL,
+       GNLD_GFX_PER_CU_CG,
+       GNLD_RM,
+       GNLD_DS_DCEFCLK,
+       GNLD_ACDC,
+       GNLD_VR0HOT,
+       GNLD_VR1HOT,
+       GNLD_FW_CTF,
+       GNLD_LED_DISPLAY,
+       GNLD_FAN_CONTROL,
+       GNLD_DIDT,
+       GNLD_GFXOFF,
+       GNLD_CG,
+       GNLD_ACG,
+
+       GNLD_FEATURES_MAX
+};
+
+
+#define GNLD_DPM_MAX    (GNLD_DPM_DCEFCLK + 1)
+
+#define SMC_DPM_FEATURES    0x30F
+
+struct smu_features {
+       bool supported;
+       bool enabled;
+       bool allowed;
+       uint32_t smu_feature_id;
+       uint64_t smu_feature_bitmap;
+};
+
+struct vega12_performance_level {
+       uint32_t  soc_clock;
+       uint32_t  gfx_clock;
+       uint32_t  mem_clock;
+};
+
+struct vega12_bacos {
+       uint32_t                       baco_flags;
+       /* struct vega12_performance_level  performance_level; */
+};
+
+struct vega12_uvd_clocks {
+       uint32_t  vclk;
+       uint32_t  dclk;
+};
+
+struct vega12_vce_clocks {
+       uint32_t  evclk;
+       uint32_t  ecclk;
+};
+
+struct vega12_power_state {
+       uint32_t                  magic;
+       struct vega12_uvd_clocks    uvd_clks;
+       struct vega12_vce_clocks    vce_clks;
+       uint16_t                  performance_level_count;
+       bool                      dc_compatible;
+       uint32_t                  sclk_threshold;
+       struct vega12_performance_level  performance_levels[VEGA12_MAX_HARDWARE_POWERLEVELS];
+};
+
+struct vega12_dpm_level {
+       bool            enabled;
+       uint32_t        value;
+       uint32_t        param1;
+};
+
+#define VEGA12_MAX_DEEPSLEEP_DIVIDER_ID 5
+#define MAX_REGULAR_DPM_NUMBER 8
+#define MAX_PCIE_CONF 2
+#define VEGA12_MINIMUM_ENGINE_CLOCK 2500
+
+struct vega12_dpm_state {
+       uint32_t  soft_min_level;
+       uint32_t  soft_max_level;
+       uint32_t  hard_min_level;
+       uint32_t  hard_max_level;
+};
+
+struct vega12_single_dpm_table {
+       uint32_t                count;
+       struct vega12_dpm_state dpm_state;
+       struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
+};
+
+struct vega12_odn_dpm_control {
+       uint32_t        count;
+       uint32_t        entries[MAX_REGULAR_DPM_NUMBER];
+};
+
+struct vega12_pcie_table {
+       uint16_t count;
+       uint8_t  pcie_gen[MAX_PCIE_CONF];
+       uint8_t  pcie_lane[MAX_PCIE_CONF];
+       uint32_t lclk[MAX_PCIE_CONF];
+};
+
+struct vega12_dpm_table {
+       struct vega12_single_dpm_table  soc_table;
+       struct vega12_single_dpm_table  gfx_table;
+       struct vega12_single_dpm_table  mem_table;
+       struct vega12_single_dpm_table  eclk_table;
+       struct vega12_single_dpm_table  vclk_table;
+       struct vega12_single_dpm_table  dclk_table;
+       struct vega12_single_dpm_table  dcef_table;
+       struct vega12_single_dpm_table  pixel_table;
+       struct vega12_single_dpm_table  display_table;
+       struct vega12_single_dpm_table  phy_table;
+       struct vega12_pcie_table        pcie_table;
+};
+
+#define VEGA12_MAX_LEAKAGE_COUNT  8
+struct vega12_leakage_voltage {
+       uint16_t  count;
+       uint16_t  leakage_id[VEGA12_MAX_LEAKAGE_COUNT];
+       uint16_t  actual_voltage[VEGA12_MAX_LEAKAGE_COUNT];
+};
+
+struct vega12_display_timing {
+       uint32_t  min_clock_in_sr;
+       uint32_t  num_existing_displays;
+};
+
+struct vega12_dpmlevel_enable_mask {
+       uint32_t  uvd_dpm_enable_mask;
+       uint32_t  vce_dpm_enable_mask;
+       uint32_t  samu_dpm_enable_mask;
+       uint32_t  sclk_dpm_enable_mask;
+       uint32_t  mclk_dpm_enable_mask;
+};
+
+struct vega12_vbios_boot_state {
+       bool        bsoc_vddc_lock;
+       uint8_t     uc_cooling_id;
+       uint16_t    vddc;
+       uint16_t    vddci;
+       uint16_t    mvddc;
+       uint16_t    vdd_gfx;
+       uint32_t    gfx_clock;
+       uint32_t    mem_clock;
+       uint32_t    soc_clock;
+       uint32_t    dcef_clock;
+};
+
+#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
+#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
+#define DPMTABLE_UPDATE_SCLK        0x00000004
+#define DPMTABLE_UPDATE_MCLK        0x00000008
+#define DPMTABLE_OD_UPDATE_VDDC     0x00000010
+
+struct vega12_smc_state_table {
+       uint32_t        soc_boot_level;
+       uint32_t        gfx_boot_level;
+       uint32_t        dcef_boot_level;
+       uint32_t        mem_boot_level;
+       uint32_t        uvd_boot_level;
+       uint32_t        vce_boot_level;
+       uint32_t        gfx_max_level;
+       uint32_t        mem_max_level;
+       uint8_t         vr_hot_gpio;
+       uint8_t         ac_dc_gpio;
+       uint8_t         therm_out_gpio;
+       uint8_t         therm_out_polarity;
+       uint8_t         therm_out_mode;
+       PPTable_t       pp_table;
+       Watermarks_t    water_marks_table;
+       AvfsDebugTable_t avfs_debug_table;
+       AvfsFuseOverride_t avfs_fuse_override_table;
+       SmuMetrics_t    smu_metrics;
+       DriverSmuConfig_t driver_smu_config;
+       DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint;
+       OverDriveTable_t overdrive_table;
+};
+
+struct vega12_mclk_latency_entries {
+       uint32_t  frequency;
+       uint32_t  latency;
+};
+
+struct vega12_mclk_latency_table {
+       uint32_t  count;
+       struct vega12_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
+};
+
+struct vega12_registry_data {
+       uint64_t  disallowed_features;
+       uint8_t   ac_dc_switch_gpio_support;
+       uint8_t   acg_loop_support;
+       uint8_t   clock_stretcher_support;
+       uint8_t   db_ramping_support;
+       uint8_t   didt_mode;
+       uint8_t   didt_support;
+       uint8_t   edc_didt_support;
+       uint8_t   force_dpm_high;
+       uint8_t   fuzzy_fan_control_support;
+       uint8_t   mclk_dpm_key_disabled;
+       uint8_t   od_state_in_dc_support;
+       uint8_t   pcie_lane_override;
+       uint8_t   pcie_speed_override;
+       uint32_t  pcie_clock_override;
+       uint8_t   pcie_dpm_key_disabled;
+       uint8_t   dcefclk_dpm_key_disabled;
+       uint8_t   prefetcher_dpm_key_disabled;
+       uint8_t   quick_transition_support;
+       uint8_t   regulator_hot_gpio_support;
+       uint8_t   master_deep_sleep_support;
+       uint8_t   gfx_clk_deep_sleep_support;
+       uint8_t   sclk_deep_sleep_support;
+       uint8_t   lclk_deep_sleep_support;
+       uint8_t   dce_fclk_deep_sleep_support;
+       uint8_t   sclk_dpm_key_disabled;
+       uint8_t   sclk_throttle_low_notification;
+       uint8_t   skip_baco_hardware;
+       uint8_t   socclk_dpm_key_disabled;
+       uint8_t   sq_ramping_support;
+       uint8_t   tcp_ramping_support;
+       uint8_t   td_ramping_support;
+       uint8_t   dbr_ramping_support;
+       uint8_t   gc_didt_support;
+       uint8_t   psm_didt_support;
+       uint8_t   thermal_support;
+       uint8_t   fw_ctf_enabled;
+       uint8_t   led_dpm_enabled;
+       uint8_t   fan_control_support;
+       uint8_t   ulv_support;
+       uint8_t   odn_feature_enable;
+       uint8_t   disable_water_mark;
+       uint8_t   disable_workload_policy;
+       uint32_t  force_workload_policy_mask;
+       uint8_t   disable_3d_fs_detection;
+       uint8_t   disable_pp_tuning;
+       uint8_t   disable_xlpp_tuning;
+       uint32_t  perf_ui_tuning_profile_turbo;
+       uint32_t  perf_ui_tuning_profile_powerSave;
+       uint32_t  perf_ui_tuning_profile_xl;
+       uint16_t  zrpm_stop_temp;
+       uint16_t  zrpm_start_temp;
+       uint32_t  stable_pstate_sclk_dpm_percentage;
+       uint8_t   fps_support;
+       uint8_t   vr0hot;
+       uint8_t   vr1hot;
+       uint8_t   disable_auto_wattman;
+       uint32_t  auto_wattman_debug;
+       uint32_t  auto_wattman_sample_period;
+       uint8_t   auto_wattman_threshold;
+       uint8_t   log_avfs_param;
+       uint8_t   enable_enginess;
+       uint8_t   custom_fan_support;
+       uint8_t   disable_pcc_limit_control;
+};
+
+struct vega12_odn_clock_voltage_dependency_table {
+       uint32_t count;
+       struct phm_ppt_v1_clock_voltage_dependency_record
+               entries[MAX_REGULAR_DPM_NUMBER];
+};
+
+struct vega12_odn_dpm_table {
+       struct vega12_odn_dpm_control           control_gfxclk_state;
+       struct vega12_odn_dpm_control           control_memclk_state;
+       struct phm_odn_clock_levels             odn_core_clock_dpm_levels;
+       struct phm_odn_clock_levels             odn_memory_clock_dpm_levels;
+       struct vega12_odn_clock_voltage_dependency_table                vdd_dependency_on_sclk;
+       struct vega12_odn_clock_voltage_dependency_table                vdd_dependency_on_mclk;
+       struct vega12_odn_clock_voltage_dependency_table                vdd_dependency_on_socclk;
+       uint32_t                                odn_mclk_min_limit;
+};
+
+struct vega12_odn_fan_table {
+       uint32_t        target_fan_speed;
+       uint32_t        target_temperature;
+       uint32_t        min_performance_clock;
+       uint32_t        min_fan_limit;
+       bool            force_fan_pwm;
+};
+
+struct vega12_hwmgr {
+       struct vega12_dpm_table          dpm_table;
+       struct vega12_dpm_table          golden_dpm_table;
+       struct vega12_registry_data      registry_data;
+       struct vega12_vbios_boot_state   vbios_boot_state;
+       struct vega12_mclk_latency_table mclk_latency_table;
+
+       struct vega12_leakage_voltage    vddc_leakage;
+
+       uint32_t                           vddc_control;
+       struct pp_atomfwctrl_voltage_table vddc_voltage_table;
+       uint32_t                           mvdd_control;
+       struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
+       uint32_t                           vddci_control;
+       struct pp_atomfwctrl_voltage_table vddci_voltage_table;
+
+       uint32_t                           active_auto_throttle_sources;
+       uint32_t                           water_marks_bitmap;
+       struct vega12_bacos                bacos;
+
+       struct vega12_odn_dpm_table       odn_dpm_table;
+       struct vega12_odn_fan_table       odn_fan_table;
+
+       /* ---- General data ---- */
+       uint8_t                           need_update_dpm_table;
+
+       bool                           cac_enabled;
+       bool                           battery_state;
+       bool                           is_tlu_enabled;
+       bool                           avfs_exist;
+
+       uint32_t                       low_sclk_interrupt_threshold;
+
+       uint32_t                       total_active_cus;
+
+       struct vega12_display_timing display_timing;
+
+       /* ---- Vega12 Dyn Register Settings ---- */
+
+       uint32_t                       debug_settings;
+       uint32_t                       lowest_uclk_reserved_for_ulv;
+       uint32_t                       gfxclk_average_alpha;
+       uint32_t                       socclk_average_alpha;
+       uint32_t                       uclk_average_alpha;
+       uint32_t                       gfx_activity_average_alpha;
+       uint32_t                       display_voltage_mode;
+       uint32_t                       dcef_clk_quad_eqn_a;
+       uint32_t                       dcef_clk_quad_eqn_b;
+       uint32_t                       dcef_clk_quad_eqn_c;
+       uint32_t                       disp_clk_quad_eqn_a;
+       uint32_t                       disp_clk_quad_eqn_b;
+       uint32_t                       disp_clk_quad_eqn_c;
+       uint32_t                       pixel_clk_quad_eqn_a;
+       uint32_t                       pixel_clk_quad_eqn_b;
+       uint32_t                       pixel_clk_quad_eqn_c;
+       uint32_t                       phy_clk_quad_eqn_a;
+       uint32_t                       phy_clk_quad_eqn_b;
+       uint32_t                       phy_clk_quad_eqn_c;
+
+       /* ---- Thermal Temperature Setting ---- */
+       struct vega12_dpmlevel_enable_mask     dpm_level_enable_mask;
+
+       /* ---- Power Gating States ---- */
+       bool                           uvd_power_gated;
+       bool                           vce_power_gated;
+       bool                           samu_power_gated;
+       bool                           need_long_memory_training;
+
+       /* Internal settings to apply the application power optimization parameters */
+       bool                           apply_optimized_settings;
+       uint32_t                       disable_dpm_mask;
+
+       /* ---- Overdrive next setting ---- */
+       uint32_t                       apply_overdrive_next_settings_mask;
+
+       /* ---- Workload Mask ---- */
+       uint32_t                       workload_mask;
+
+       /* ---- SMU9 ---- */
+       uint32_t                       smu_version;
+       struct smu_features            smu_features[GNLD_FEATURES_MAX];
+       struct vega12_smc_state_table  smc_state_table;
+};
+
+#define VEGA12_DPM2_NEAR_TDP_DEC                      10
+#define VEGA12_DPM2_ABOVE_SAFE_INC                    5
+#define VEGA12_DPM2_BELOW_SAFE_INC                    20
+
+#define VEGA12_DPM2_LTA_WINDOW_SIZE                   7
+
+#define VEGA12_DPM2_LTS_TRUNCATE                      0
+
+#define VEGA12_DPM2_TDP_SAFE_LIMIT_PERCENT            80
+
+#define VEGA12_DPM2_MAXPS_PERCENT_M                   90
+#define VEGA12_DPM2_MAXPS_PERCENT_H                   90
+
+#define VEGA12_DPM2_PWREFFICIENCYRATIO_MARGIN         50
+
+#define VEGA12_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
+#define VEGA12_DPM2_SQ_RAMP_MIN_POWER                 0x12
+#define VEGA12_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
+#define VEGA12_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
+#define VEGA12_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
+
+#define VEGA12_VOLTAGE_CONTROL_NONE                   0x0
+#define VEGA12_VOLTAGE_CONTROL_BY_GPIO                0x1
+#define VEGA12_VOLTAGE_CONTROL_BY_SVID2               0x2
+#define VEGA12_VOLTAGE_CONTROL_MERGED                 0x3
+/* To convert to Q8.8 format for firmware */
+#define VEGA12_Q88_FORMAT_CONVERSION_UNIT             256
+
+#define VEGA12_UNUSED_GPIO_PIN       0x7F
+
+#define VEGA12_THERM_OUT_MODE_DISABLE       0x0
+#define VEGA12_THERM_OUT_MODE_THERM_ONLY    0x1
+#define VEGA12_THERM_OUT_MODE_THERM_VRHOT   0x2
+
+#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT   0xffffffff
+#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT    0xffffffff
+
+#define PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
+#define PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
+#define PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT      25 /* 10% * 255 = 25 */
+#define PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT  25 /* 10% * 255 = 25 */
+#define PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT   0xffffffff
+#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT         0xffffffff
+#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT          0xffffffff
+
+#define VEGA12_UMD_PSTATE_GFXCLK_LEVEL         0x3
+#define VEGA12_UMD_PSTATE_SOCCLK_LEVEL         0x3
+#define VEGA12_UMD_PSTATE_MCLK_LEVEL           0x2
+
+int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
+
+#endif /* _VEGA12_HWMGR_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_powertune.c
new file mode 100644 (file)
index 0000000..76e60c0
--- /dev/null
@@ -0,0 +1,1364 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "hwmgr.h"
+#include "vega12_hwmgr.h"
+#include "vega12_powertune.h"
+#include "vega12_smumgr.h"
+#include "vega12_ppsmc.h"
+#include "vega12_inc.h"
+#include "pp_debug.h"
+#include "pp_soc15.h"
+
+static const struct vega12_didt_config_reg SEDiDtTuningCtrlConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* DIDT_SQ */
+       {   ixDIDT_SQ_TUNING_CTRL,             DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,        DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,        0x3853 },
+       {   ixDIDT_SQ_TUNING_CTRL,             DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,        DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,        0x3153 },
+
+       /* DIDT_TD */
+       {   ixDIDT_TD_TUNING_CTRL,             DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,        DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,        0x0dde },
+       {   ixDIDT_TD_TUNING_CTRL,             DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,        DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,        0x0dde },
+
+       /* DIDT_TCP */
+       {   ixDIDT_TCP_TUNING_CTRL,            DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,       DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,       0x3dde },
+       {   ixDIDT_TCP_TUNING_CTRL,            DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,       DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,       0x3dde },
+
+       /* DIDT_DB */
+       {   ixDIDT_DB_TUNING_CTRL,             DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,        DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,        0x3dde },
+       {   ixDIDT_DB_TUNING_CTRL,             DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,        DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,        0x3dde },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SEDiDtCtrl3Config_vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset               Mask                                                     Shift                                                            Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /*DIDT_SQ_CTRL3 */
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK,       DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT,             0x0000 },
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,       DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,             0x0000 },
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK,       DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT,             0x0003 },
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,       DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,             0x0000 },
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,       DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,             0x0000 },
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,       DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,             0x0003 },
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,       DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,       DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK,       DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT,             0x0000 },
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK,       DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT,             0x0000 },
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK,       DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT,             0x0000 },
+       {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK,       DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,             0x0000 },
+
+       /*DIDT_TCP_CTRL3 */
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK,      DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT,            0x0000 },
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,      DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,            0x0000 },
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK,      DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT,            0x0003 },
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,      DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,            0x0000 },
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,      DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,            0x0000 },
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,      DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,            0x0003 },
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,      DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,            0x0000 },
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,      DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,            0x0000 },
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK,      DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT,            0x0000 },
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK,      DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT,            0x0000 },
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK,      DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT,            0x0000 },
+       {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK,      DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,            0x0000 },
+
+       /*DIDT_TD_CTRL3 */
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK,       DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT,             0x0000 },
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,       DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,             0x0000 },
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__THROTTLE_POLICY_MASK,       DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT,             0x0003 },
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,       DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,             0x0000 },
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,       DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,             0x0000 },
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,       DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,             0x0003 },
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,       DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,       DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK,       DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT,             0x0000 },
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK,       DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT,             0x0000 },
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK,       DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT,             0x0000 },
+       {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK,       DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,             0x0000 },
+
+       /*DIDT_DB_CTRL3 */
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK,       DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT,             0x0000 },
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,       DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,             0x0000 },
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__THROTTLE_POLICY_MASK,       DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT,             0x0003 },
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,       DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,             0x0000 },
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,       DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,             0x0000 },
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,       DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,             0x0003 },
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,       DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,       DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK,       DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT,             0x0000 },
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK,       DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT,             0x0000 },
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK,       DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT,             0x0000 },
+       {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK,       DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,             0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SEDiDtCtrl2Config_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                            Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* DIDT_SQ */
+       {   ixDIDT_SQ_CTRL2,                  DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK,                 DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT,                 0x3853 },
+       {   ixDIDT_SQ_CTRL2,                  DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,        DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,        0x00c0 },
+       {   ixDIDT_SQ_CTRL2,                  DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,        DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,        0x0000 },
+
+       /* DIDT_TD */
+       {   ixDIDT_TD_CTRL2,                  DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK,                 DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT,                 0x3fff },
+       {   ixDIDT_TD_CTRL2,                  DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,        DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,        0x00c0 },
+       {   ixDIDT_TD_CTRL2,                  DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,        DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,        0x0001 },
+
+       /* DIDT_TCP */
+       {   ixDIDT_TCP_CTRL2,                 DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK,                DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT,                0x3dde },
+       {   ixDIDT_TCP_CTRL2,                 DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,       DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,       0x00c0 },
+       {   ixDIDT_TCP_CTRL2,                 DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,       DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,       0x0001 },
+
+       /* DIDT_DB */
+       {   ixDIDT_DB_CTRL2,                  DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK,                 DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT,                 0x3dde },
+       {   ixDIDT_DB_CTRL2,                  DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,        DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,        0x00c0 },
+       {   ixDIDT_DB_CTRL2,                  DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,        DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,        0x0001 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SEDiDtCtrl1Config_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* DIDT_SQ */
+       {   ixDIDT_SQ_CTRL1,                   DIDT_SQ_CTRL1__MIN_POWER_MASK,                       DIDT_SQ_CTRL1__MIN_POWER__SHIFT,                       0x0000 },
+       {   ixDIDT_SQ_CTRL1,                   DIDT_SQ_CTRL1__MAX_POWER_MASK,                       DIDT_SQ_CTRL1__MAX_POWER__SHIFT,                       0xffff },
+       /* DIDT_TD */
+       {   ixDIDT_TD_CTRL1,                   DIDT_TD_CTRL1__MIN_POWER_MASK,                       DIDT_TD_CTRL1__MIN_POWER__SHIFT,                       0x0000 },
+       {   ixDIDT_TD_CTRL1,                   DIDT_TD_CTRL1__MAX_POWER_MASK,                       DIDT_TD_CTRL1__MAX_POWER__SHIFT,                       0xffff },
+       /* DIDT_TCP */
+       {   ixDIDT_TCP_CTRL1,                  DIDT_TCP_CTRL1__MIN_POWER_MASK,                      DIDT_TCP_CTRL1__MIN_POWER__SHIFT,                      0x0000 },
+       {   ixDIDT_TCP_CTRL1,                  DIDT_TCP_CTRL1__MAX_POWER_MASK,                      DIDT_TCP_CTRL1__MAX_POWER__SHIFT,                      0xffff },
+       /* DIDT_DB */
+       {   ixDIDT_DB_CTRL1,                   DIDT_DB_CTRL1__MIN_POWER_MASK,                       DIDT_DB_CTRL1__MIN_POWER__SHIFT,                       0x0000 },
+       {   ixDIDT_DB_CTRL1,                   DIDT_DB_CTRL1__MAX_POWER_MASK,                       DIDT_DB_CTRL1__MAX_POWER__SHIFT,                       0xffff },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+
+static const struct vega12_didt_config_reg SEDiDtWeightConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                  Shift                                                 Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* DIDT_SQ */
+       {   ixDIDT_SQ_WEIGHT0_3,               0xFFFFFFFF,                                           0,                                                    0x2B363B1A },
+       {   ixDIDT_SQ_WEIGHT4_7,               0xFFFFFFFF,                                           0,                                                    0x270B2432 },
+       {   ixDIDT_SQ_WEIGHT8_11,              0xFFFFFFFF,                                           0,                                                    0x00000018 },
+
+       /* DIDT_TD */
+       {   ixDIDT_TD_WEIGHT0_3,               0xFFFFFFFF,                                           0,                                                    0x2B1D220F },
+       {   ixDIDT_TD_WEIGHT4_7,               0xFFFFFFFF,                                           0,                                                    0x00007558 },
+       {   ixDIDT_TD_WEIGHT8_11,              0xFFFFFFFF,                                           0,                                                    0x00000000 },
+
+       /* DIDT_TCP */
+       {   ixDIDT_TCP_WEIGHT0_3,               0xFFFFFFFF,                                          0,                                                    0x5ACE160D },
+       {   ixDIDT_TCP_WEIGHT4_7,               0xFFFFFFFF,                                          0,                                                    0x00000000 },
+       {   ixDIDT_TCP_WEIGHT8_11,              0xFFFFFFFF,                                          0,                                                    0x00000000 },
+
+       /* DIDT_DB */
+       {   ixDIDT_DB_WEIGHT0_3,                0xFFFFFFFF,                                          0,                                                    0x0E152A0F },
+       {   ixDIDT_DB_WEIGHT4_7,                0xFFFFFFFF,                                          0,                                                    0x09061813 },
+       {   ixDIDT_DB_WEIGHT8_11,               0xFFFFFFFF,                                          0,                                                    0x00000013 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SEDiDtCtrl0Config_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* DIDT_SQ */
+       {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK,   DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
+       {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__PHASE_OFFSET_MASK,   DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
+       {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK,   DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT,  0x0000 },
+       {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
+       {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT,  0x0001 },
+       {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK,   DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT,  0x0001 },
+       {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT,  0x0001 },
+       {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,   DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT,  0xffff },
+       {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK,   DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT,  0x0000 },
+       {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT,  0x0000 },
+       {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT,  0x0000 },
+       /* DIDT_TD */
+       {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK,   DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
+       {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__PHASE_OFFSET_MASK,   DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
+       {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK,   DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT,  0x0000 },
+       {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
+       {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK,   DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT,  0x0001 },
+       {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK,   DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT,  0x0001 },
+       {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,   DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT,  0x0001 },
+       {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,   DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT,  0xffff },
+       {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK,   DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT,  0x0000 },
+       {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK,   DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT,  0x0000 },
+       {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,   DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT,  0x0000 },
+       /* DIDT_TCP */
+       {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK,  DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
+       {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__PHASE_OFFSET_MASK,  DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
+       {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK,  DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
+       {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,  DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
+       {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
+       {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK,  DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
+       {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
+       {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,  DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
+       {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK,  DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
+       {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
+       {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
+       /* DIDT_DB */
+       {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK,   DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
+       {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__PHASE_OFFSET_MASK,   DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
+       {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK,   DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT,  0x0000 },
+       {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
+       {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK,   DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT,  0x0001 },
+       {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK,   DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT,  0x0001 },
+       {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,   DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT,  0x0001 },
+       {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,   DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT,  0xffff },
+       {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK,   DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT,  0x0000 },
+       {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK,   DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT,  0x0000 },
+       {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,   DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT,  0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+
+static const struct vega12_didt_config_reg SEDiDtStallCtrlConfig_vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                   Mask                                                     Shift                                                      Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* DIDT_SQ */
+       {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,     0x0004 },
+       {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,     0x0004 },
+       {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,     0x000a },
+       {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,     0x000a },
+
+       /* DIDT_TD */
+       {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,     0x0001 },
+       {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,     0x0001 },
+       {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,     0x000a },
+       {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,     0x000a },
+
+       /* DIDT_TCP */
+       {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,    0x0001 },
+       {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,    0x0001 },
+       {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,    0x000a },
+       {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,    0x000a },
+
+       /* DIDT_DB */
+       {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,     0x0004 },
+       {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,     0x0004 },
+       {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,     0x000a },
+       {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,     0x000a },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SEDiDtStallPatternConfig_vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                        Mask                                                      Shift                                                    Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* DIDT_SQ_STALL_PATTERN_1_2 */
+       {   ixDIDT_SQ_STALL_PATTERN_1_2,  DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,    DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT,  0x0001 },
+       {   ixDIDT_SQ_STALL_PATTERN_1_2,  DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,    DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT,  0x0001 },
+
+       /* DIDT_SQ_STALL_PATTERN_3_4 */
+       {   ixDIDT_SQ_STALL_PATTERN_3_4,  DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,    DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT,  0x0001 },
+       {   ixDIDT_SQ_STALL_PATTERN_3_4,  DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,    DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT,  0x0001 },
+
+       /* DIDT_SQ_STALL_PATTERN_5_6 */
+       {   ixDIDT_SQ_STALL_PATTERN_5_6,  DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,    DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT,  0x0000 },
+       {   ixDIDT_SQ_STALL_PATTERN_5_6,  DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,    DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT,  0x0000 },
+
+       /* DIDT_SQ_STALL_PATTERN_7 */
+       {   ixDIDT_SQ_STALL_PATTERN_7,    DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,      DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,    0x0000 },
+
+       /* DIDT_TCP_STALL_PATTERN_1_2 */
+       {   ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,   DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
+       {   ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,   DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
+
+       /* DIDT_TCP_STALL_PATTERN_3_4 */
+       {   ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,   DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
+       {   ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,   DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
+
+       /* DIDT_TCP_STALL_PATTERN_5_6 */
+       {   ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,   DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
+       {   ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,   DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
+
+       /* DIDT_TCP_STALL_PATTERN_7 */
+       {   ixDIDT_TCP_STALL_PATTERN_7,   DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,     DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,   0x0000 },
+
+       /* DIDT_TD_STALL_PATTERN_1_2 */
+       {   ixDIDT_TD_STALL_PATTERN_1_2,  DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,    DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT,  0x0001 },
+       {   ixDIDT_TD_STALL_PATTERN_1_2,  DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,    DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT,  0x0001 },
+
+       /* DIDT_TD_STALL_PATTERN_3_4 */
+       {   ixDIDT_TD_STALL_PATTERN_3_4,  DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,    DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT,  0x0001 },
+       {   ixDIDT_TD_STALL_PATTERN_3_4,  DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,    DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT,  0x0001 },
+
+       /* DIDT_TD_STALL_PATTERN_5_6 */
+       {   ixDIDT_TD_STALL_PATTERN_5_6,  DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,    DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT,  0x0000 },
+       {   ixDIDT_TD_STALL_PATTERN_5_6,  DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,    DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT,  0x0000 },
+
+       /* DIDT_TD_STALL_PATTERN_7 */
+       {   ixDIDT_TD_STALL_PATTERN_7,    DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,      DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,    0x0000 },
+
+       /* DIDT_DB_STALL_PATTERN_1_2 */
+       {   ixDIDT_DB_STALL_PATTERN_1_2,  DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,    DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT,  0x0001 },
+       {   ixDIDT_DB_STALL_PATTERN_1_2,  DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,    DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT,  0x0001 },
+
+       /* DIDT_DB_STALL_PATTERN_3_4 */
+       {   ixDIDT_DB_STALL_PATTERN_3_4,  DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,    DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT,  0x0001 },
+       {   ixDIDT_DB_STALL_PATTERN_3_4,  DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,    DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT,  0x0001 },
+
+       /* DIDT_DB_STALL_PATTERN_5_6 */
+       {   ixDIDT_DB_STALL_PATTERN_5_6,  DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,    DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT,  0x0000 },
+       {   ixDIDT_DB_STALL_PATTERN_5_6,  DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,    DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT,  0x0000 },
+
+       /* DIDT_DB_STALL_PATTERN_7 */
+       {   ixDIDT_DB_STALL_PATTERN_7,    DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,      DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,    0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SELCacConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ */
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00060021 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00860021 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01060021 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01860021 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x02060021 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x02860021 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x03060021 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x03860021 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x04060021 },
+       /* TD */
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x000E0020 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x008E0020 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x010E0020 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x018E0020 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x020E0020 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x028E0020 },
+       /* TCP */
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x001c0020 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x009c0020 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x011c0020 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x019c0020 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x021c0020 },
+       /* DB */
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00200008 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00820008 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01020008 },
+       {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01820008 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+
+static const struct vega12_didt_config_reg SEEDCStallPatternConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ */
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00030001 },
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x000F0007 },
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x003F001F },
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x0000007F },
+       /* TD */
+       {   ixDIDT_TD_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_TD_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_TD_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_TD_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       /* TCP */
+       {   ixDIDT_TCP_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                         0,                                                     0x00000000 },
+       {   ixDIDT_TCP_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                         0,                                                     0x00000000 },
+       {   ixDIDT_TCP_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                         0,                                                     0x00000000 },
+       {   ixDIDT_TCP_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                         0,                                                     0x00000000 },
+       /* DB */
+       {   ixDIDT_DB_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_DB_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_DB_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_DB_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SEEDCForceStallPatternConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ */
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000015 },
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       /* TD */
+       {   ixDIDT_TD_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000015 },
+       {   ixDIDT_TD_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_TD_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_TD_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SEEDCStallDelayConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ */
+       {   ixDIDT_SQ_EDC_STALL_DELAY_1,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_SQ_EDC_STALL_DELAY_2,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       /* TD */
+       {   ixDIDT_TD_EDC_STALL_DELAY_1,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_TD_EDC_STALL_DELAY_2,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       /* TCP */
+       {   ixDIDT_TCP_EDC_STALL_DELAY_1,      0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       {   ixDIDT_TCP_EDC_STALL_DELAY_2,      0xFFFFFFFF,                                          0,                                                     0x00000000 },
+       /* DB */
+       {   ixDIDT_DB_EDC_STALL_DELAY_1,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SEEDCThresholdConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       {   ixDIDT_SQ_EDC_THRESHOLD,           0xFFFFFFFF,                                          0,                                                     0x0000010E },
+       {   ixDIDT_TD_EDC_THRESHOLD,           0xFFFFFFFF,                                          0,                                                     0xFFFFFFFF },
+       {   ixDIDT_TCP_EDC_THRESHOLD,          0xFFFFFFFF,                                          0,                                                     0xFFFFFFFF },
+       {   ixDIDT_DB_EDC_THRESHOLD,           0xFFFFFFFF,                                          0,                                                     0xFFFFFFFF },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SEEDCCtrlResetConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ */
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0001 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SEEDCCtrlConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ */
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0001 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0004 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x0006 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg SEEDCCtrlForceStallConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ */
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0001 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0001 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x000C },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
+
+       /* TD */
+       {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_EN_MASK,                       DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
+       {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
+       {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
+       {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0001 },
+       {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0001 },
+       {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x000E },
+       {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
+       {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
+       {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
+       {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
+       {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg    GCDiDtDroopCtrlConfig_vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT,  0x0000 },
+       {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT,  0x0000 },
+       {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT,  0x0000 },
+       {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK,   GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT,  0x0000 },
+       {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT,  0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg    GCDiDtCtrl0Config_vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK,   GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
+       {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__PHASE_OFFSET_MASK,   GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
+       {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_SW_RST_MASK,   GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT,  0x0000 },
+       {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
+       {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,   GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,  0x0000 },
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+
+static const struct vega12_didt_config_reg   PSMSEEDCStallPatternConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ EDC STALL PATTERNs */
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,  DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK,   DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT,   0x0101 },
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,  DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK,   DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT,   0x0101 },
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,  DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK,   DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT,   0x1111 },
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,  DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK,   DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT,   0x1111 },
+
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,  DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK,   DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT,   0x1515 },
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,  DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK,   DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT,   0x1515 },
+
+       {   ixDIDT_SQ_EDC_STALL_PATTERN_7,  DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK,   DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT,     0x5555 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg   PSMSEEDCStallDelayConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ EDC STALL DELAYs */
+       {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT,  0x0000 },
+       {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT,  0x0000 },
+       {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT,  0x0000 },
+       {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT,  0x0000 },
+
+       {   ixDIDT_SQ_EDC_STALL_DELAY_2,      DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK,  DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT,  0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg   PSMSEEDCThresholdConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ EDC THRESHOLD */
+       {   ixDIDT_SQ_EDC_THRESHOLD,           DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK,           DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT,            0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg   PSMSEEDCCtrlResetConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ EDC CTRL */
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0001 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg   PSMSEEDCCtrlConfig_Vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       /* SQ EDC CTRL */
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0001 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x000E },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0001 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0003 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
+       {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg   PSMGCEDCThresholdConfig_vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       {   mmGC_EDC_THRESHOLD,                GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK,                GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT,                 0x0000000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg   PSMGCEDCDroopCtrlConfig_vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK,          GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT,           0x0001 },
+       {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK,         GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT,          0x0384 },
+       {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK,       GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT,        0x0001 },
+       {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK,                 GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT,                  0x0001 },
+       {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK,               GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT,                0x0001 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg   PSMGCEDCCtrlResetConfig_vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_EN_MASK,                            GC_EDC_CTRL__EDC_EN__SHIFT,                             0x0000 },
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_SW_RST_MASK,                        GC_EDC_CTRL__EDC_SW_RST__SHIFT,                         0x0001 },
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,               GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,                0x0000 },
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_FORCE_STALL_MASK,                   GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT,                    0x0000 },
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,       GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,        0x0000 },
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,          GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,           0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg   PSMGCEDCCtrlConfig_vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_EN_MASK,                            GC_EDC_CTRL__EDC_EN__SHIFT,                             0x0001 },
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_SW_RST_MASK,                        GC_EDC_CTRL__EDC_SW_RST__SHIFT,                         0x0000 },
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,               GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,                0x0000 },
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_FORCE_STALL_MASK,                   GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT,                    0x0000 },
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,       GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,        0x0000 },
+       {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,          GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,           0x0000 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg    AvfsPSMResetConfig_vega12[]=
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       {   0x16A02,                         0xFFFFFFFF,                                            0x0,                                                    0x0000005F },
+       {   0x16A05,                         0xFFFFFFFF,                                            0x0,                                                    0x00000001 },
+       {   0x16A06,                         0x00000001,                                            0x0,                                                    0x02000000 },
+       {   0x16A01,                         0xFFFFFFFF,                                            0x0,                                                    0x00003027 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static const struct vega12_didt_config_reg    AvfsPSMInitConfig_vega12[] =
+{
+/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ *      Offset                             Mask                                                 Shift                                                  Value
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+       {   0x16A05,                         0xFFFFFFFF,                                            0x18,                                                    0x00000001 },
+       {   0x16A05,                         0xFFFFFFFF,                                            0x8,                                                     0x00000003 },
+       {   0x16A05,                         0xFFFFFFFF,                                            0xa,                                                     0x00000006 },
+       {   0x16A05,                         0xFFFFFFFF,                                            0x7,                                                     0x00000000 },
+       {   0x16A06,                         0xFFFFFFFF,                                            0x18,                                                    0x00000001 },
+       {   0x16A06,                         0xFFFFFFFF,                                            0x19,                                                    0x00000001 },
+       {   0x16A01,                         0xFFFFFFFF,                                            0x0,                                                     0x00003027 },
+
+       {   0xFFFFFFFF  }  /* End of list */
+};
+
+static int vega12_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega12_didt_config_reg *config_regs, enum vega12_didt_config_reg_type reg_type)
+{
+       uint32_t data;
+
+       PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega12_program_didt_config_registers] Invalid config register table!", return -EINVAL);
+
+       while (config_regs->offset != 0xFFFFFFFF) {
+               switch (reg_type) {
+               case VEGA12_CONFIGREG_DIDT:
+                       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
+                       data &= ~config_regs->mask;
+                       data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
+                       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
+                       break;
+               case VEGA12_CONFIGREG_GCCAC:
+                       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
+                       data &= ~config_regs->mask;
+                       data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
+                       cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
+                       break;
+               case VEGA12_CONFIGREG_SECAC:
+                       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset);
+                       data &= ~config_regs->mask;
+                       data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
+                       cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data);
+                       break;
+               default:
+                       return -EINVAL;
+               }
+
+               config_regs++;
+       }
+
+       return 0;
+}
+
+static int vega12_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega12_didt_config_reg *config_regs)
+{
+       uint32_t data;
+
+       while (config_regs->offset != 0xFFFFFFFF) {
+               data = cgs_read_register(hwmgr->device, config_regs->offset);
+               data &= ~config_regs->mask;
+               data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
+               cgs_write_register(hwmgr->device, config_regs->offset, data);
+               config_regs++;
+       }
+
+       return 0;
+}
+
+static void vega12_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
+{
+       uint32_t data;
+       int result;
+       uint32_t en = (enable ? 1 : 0);
+       uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
+
+       if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
+               CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+                                    DIDT_SQ_CTRL0, DIDT_CTRL_EN, en);
+               didt_block_info &= ~SQ_Enable_MASK;
+               didt_block_info |= en << SQ_Enable_SHIFT;
+       }
+
+       if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
+               CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+                                    DIDT_DB_CTRL0, DIDT_CTRL_EN, en);
+               didt_block_info &= ~DB_Enable_MASK;
+               didt_block_info |= en << DB_Enable_SHIFT;
+       }
+
+       if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
+               CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+                                    DIDT_TD_CTRL0, DIDT_CTRL_EN, en);
+               didt_block_info &= ~TD_Enable_MASK;
+               didt_block_info |= en << TD_Enable_SHIFT;
+       }
+
+       if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
+               CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+                                    DIDT_TCP_CTRL0, DIDT_CTRL_EN, en);
+               didt_block_info &= ~TCP_Enable_MASK;
+               didt_block_info |= en << TCP_Enable_SHIFT;
+       }
+
+#if 0
+       if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
+               CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
+                                    DIDT_DBR_CTRL0, DIDT_CTRL_EN, en);
+       }
+#endif
+
+       if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {
+               if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
+                       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
+                       data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
+                       data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
+                       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
+               }
+
+               if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
+                       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
+                       data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
+                       data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
+                       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
+               }
+
+               if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
+                       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
+                       data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
+                       data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
+                       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
+               }
+
+               if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
+                       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
+                       data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
+                       data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
+                       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
+               }
+
+#if 0
+               if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
+                       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
+                       data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
+                       data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
+                       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
+               }
+#endif
+       }
+
+       if (enable) {
+               /* For Vega12, SMC does not support any mask yet. */
+               result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
+               PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!");
+       }
+}
+
+static int vega12_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
+{
+       int result;
+       uint32_t num_se = 0, count, data;
+       struct amdgpu_device *adev = hwmgr->adev;
+       uint32_t reg;
+
+       num_se = adev->gfx.config.max_shader_engines;
+
+       cgs_enter_safe_mode(hwmgr->device, true);
+
+       cgs_lock_grbm_idx(hwmgr->device, true);
+       reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
+       for (count = 0; count < num_se; count++) {
+               data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
+               cgs_write_register(hwmgr->device, reg, data);
+
+               result =  vega12_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEDiDtCtrl1Config_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEDiDtCtrl2Config_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEDiDtTuningCtrlConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SELCacConfig_Vega12, VEGA12_CONFIGREG_SECAC);
+               result |= vega12_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega12, VEGA12_CONFIGREG_DIDT);
+
+               if (0 != result)
+                       break;
+       }
+       cgs_write_register(hwmgr->device, reg, 0xE0000000);
+       cgs_lock_grbm_idx(hwmgr->device, false);
+
+       vega12_didt_set_mask(hwmgr, true);
+
+       cgs_enter_safe_mode(hwmgr->device, false);
+
+       return 0;
+}
+
+static int vega12_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
+{
+       cgs_enter_safe_mode(hwmgr->device, true);
+
+       vega12_didt_set_mask(hwmgr, false);
+
+       cgs_enter_safe_mode(hwmgr->device, false);
+
+       return 0;
+}
+
+static int vega12_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
+{
+       int result;
+       uint32_t num_se = 0, count, data;
+       struct amdgpu_device *adev = hwmgr->adev;
+       uint32_t reg;
+
+       num_se = adev->gfx.config.max_shader_engines;
+
+       cgs_enter_safe_mode(hwmgr->device, true);
+
+       cgs_lock_grbm_idx(hwmgr->device, true);
+       reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
+       for (count = 0; count < num_se; count++) {
+               data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
+               cgs_write_register(hwmgr->device, reg, data);
+
+               result = vega12_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega12, VEGA12_CONFIGREG_DIDT);
+               if (0 != result)
+                       break;
+       }
+       cgs_write_register(hwmgr->device, reg, 0xE0000000);
+       cgs_lock_grbm_idx(hwmgr->device, false);
+
+       vega12_didt_set_mask(hwmgr, true);
+
+       cgs_enter_safe_mode(hwmgr->device, false);
+
+       vega12_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega12);
+       if (PP_CAP(PHM_PlatformCaps_GCEDC))
+               vega12_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega12);
+
+       if (PP_CAP(PHM_PlatformCaps_PSM))
+               vega12_program_gc_didt_config_registers(hwmgr,  AvfsPSMInitConfig_vega12);
+
+       return 0;
+}
+
+static int vega12_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
+{
+       uint32_t data;
+
+       cgs_enter_safe_mode(hwmgr->device, true);
+
+       vega12_didt_set_mask(hwmgr, false);
+
+       cgs_enter_safe_mode(hwmgr->device, false);
+
+       if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
+               data = 0x00000000;
+               cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
+       }
+
+       if (PP_CAP(PHM_PlatformCaps_PSM))
+               vega12_program_gc_didt_config_registers(hwmgr,  AvfsPSMResetConfig_vega12);
+
+       return 0;
+}
+
+static int vega12_enable_se_edc_config(struct pp_hwmgr *hwmgr)
+{
+       int result;
+       uint32_t num_se = 0, count, data;
+       struct amdgpu_device *adev = hwmgr->adev;
+       uint32_t reg;
+
+       num_se = adev->gfx.config.max_shader_engines;
+
+       cgs_enter_safe_mode(hwmgr->device, true);
+
+       cgs_lock_grbm_idx(hwmgr->device, true);
+       reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
+       for (count = 0; count < num_se; count++) {
+               data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
+               cgs_write_register(hwmgr->device, reg, data);
+               result = vega12_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEEDCThresholdConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEEDCCtrlResetConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, SEEDCCtrlConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+
+               if (0 != result)
+                       break;
+       }
+       cgs_write_register(hwmgr->device, reg, 0xE0000000);
+       cgs_lock_grbm_idx(hwmgr->device, false);
+
+       vega12_didt_set_mask(hwmgr, true);
+
+       cgs_enter_safe_mode(hwmgr->device, false);
+
+       return 0;
+}
+
+static int vega12_disable_se_edc_config(struct pp_hwmgr *hwmgr)
+{
+       cgs_enter_safe_mode(hwmgr->device, true);
+
+       vega12_didt_set_mask(hwmgr, false);
+
+       cgs_enter_safe_mode(hwmgr->device, false);
+
+       return 0;
+}
+
+static int vega12_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
+{
+       int result;
+       uint32_t num_se = 0;
+       uint32_t count, data;
+       struct amdgpu_device *adev = hwmgr->adev;
+       uint32_t reg;
+
+       num_se = adev->gfx.config.max_shader_engines;
+
+       cgs_enter_safe_mode(hwmgr->device, true);
+
+       vega12_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega12);
+
+       cgs_lock_grbm_idx(hwmgr->device, true);
+       reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
+       for (count = 0; count < num_se; count++) {
+               data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
+               cgs_write_register(hwmgr->device, reg, data);
+               result |= vega12_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+               result |= vega12_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+
+               if (0 != result)
+                       break;
+       }
+       cgs_write_register(hwmgr->device, reg, 0xE0000000);
+       cgs_lock_grbm_idx(hwmgr->device, false);
+
+       vega12_didt_set_mask(hwmgr, true);
+
+       cgs_enter_safe_mode(hwmgr->device, false);
+
+       vega12_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega12);
+
+       if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
+               vega12_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega12);
+               vega12_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega12);
+       }
+
+       if (PP_CAP(PHM_PlatformCaps_PSM))
+               vega12_program_gc_didt_config_registers(hwmgr,  AvfsPSMInitConfig_vega12);
+
+       return 0;
+}
+
+static int vega12_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
+{
+       uint32_t data;
+
+       cgs_enter_safe_mode(hwmgr->device, true);
+
+       vega12_didt_set_mask(hwmgr, false);
+
+       cgs_enter_safe_mode(hwmgr->device, false);
+
+       if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
+               data = 0x00000000;
+               cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
+       }
+
+       if (PP_CAP(PHM_PlatformCaps_PSM))
+               vega12_program_gc_didt_config_registers(hwmgr,  AvfsPSMResetConfig_vega12);
+
+       return 0;
+}
+
+static int vega12_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
+{
+       uint32_t reg;
+       int result;
+
+       cgs_enter_safe_mode(hwmgr->device, true);
+
+       cgs_lock_grbm_idx(hwmgr->device, true);
+       reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
+       cgs_write_register(hwmgr->device, reg, 0xE0000000);
+       cgs_lock_grbm_idx(hwmgr->device, false);
+
+       result = vega12_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+       result |= vega12_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega12, VEGA12_CONFIGREG_DIDT);
+       if (0 != result)
+               return result;
+
+       vega12_didt_set_mask(hwmgr, false);
+
+       cgs_enter_safe_mode(hwmgr->device, false);
+
+       return 0;
+}
+
+static int vega12_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
+{
+       int result;
+
+       result = vega12_disable_se_edc_config(hwmgr);
+       PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result);
+
+       return 0;
+}
+
+int vega12_enable_didt_config(struct pp_hwmgr *hwmgr)
+{
+       int result = 0;
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (data->smu_features[GNLD_DIDT].supported) {
+               if (data->smu_features[GNLD_DIDT].enabled)
+                       PP_DBG_LOG("[EnableDiDtConfig] Feature DiDt Already enabled!\n");
+
+               switch (data->registry_data.didt_mode) {
+               case 0:
+                       result = vega12_enable_cac_driving_se_didt_config(hwmgr);
+                       PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result);
+                       break;
+               case 2:
+                       result = vega12_enable_psm_gc_didt_config(hwmgr);
+                       PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result);
+                       break;
+               case 3:
+                       result = vega12_enable_se_edc_config(hwmgr);
+                       PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result);
+                       break;
+               case 1:
+               case 4:
+               case 5:
+                       result = vega12_enable_psm_gc_edc_config(hwmgr);
+                       PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result);
+                       break;
+               case 6:
+                       result = vega12_enable_se_edc_force_stall_config(hwmgr);
+                       PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result);
+                       break;
+               default:
+                       result = -EINVAL;
+                       break;
+               }
+
+#if 0
+               if (0 == result) {
+                       result = vega12_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
+                       PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
+                       data->smu_features[GNLD_DIDT].enabled = true;
+               }
+#endif
+       }
+
+       return result;
+}
+
+int vega12_disable_didt_config(struct pp_hwmgr *hwmgr)
+{
+       int result = 0;
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (data->smu_features[GNLD_DIDT].supported) {
+               if (!data->smu_features[GNLD_DIDT].enabled)
+                       PP_DBG_LOG("[DisableDiDtConfig] Feature DiDt Already Disabled!\n");
+
+               switch (data->registry_data.didt_mode) {
+               case 0:
+                       result = vega12_disable_cac_driving_se_didt_config(hwmgr);
+                       PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result);
+                       break;
+               case 2:
+                       result = vega12_disable_psm_gc_didt_config(hwmgr);
+                       PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result);
+                       break;
+               case 3:
+                       result = vega12_disable_se_edc_config(hwmgr);
+                       PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result);
+                       break;
+               case 1:
+               case 4:
+               case 5:
+                       result = vega12_disable_psm_gc_edc_config(hwmgr);
+                       PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result);
+                       break;
+               case 6:
+                       result = vega12_disable_se_edc_force_stall_config(hwmgr);
+                       PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result);
+                       break;
+               default:
+                       result = -EINVAL;
+                       break;
+               }
+
+               if (0 == result) {
+                       result = vega12_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
+                       PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
+                       data->smu_features[GNLD_DIDT].enabled = false;
+               }
+       }
+
+       return result;
+}
+
+int vega12_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (data->smu_features[GNLD_PPT].enabled)
+               return smum_send_msg_to_smc_with_parameter(hwmgr,
+                               PPSMC_MSG_SetPptLimit, n);
+
+       return 0;
+}
+
+int vega12_enable_power_containment(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+       struct phm_ppt_v2_information *table_info =
+                       (struct phm_ppt_v2_information *)(hwmgr->pptable);
+       struct phm_tdp_table *tdp_table = table_info->tdp_table;
+       uint32_t default_pwr_limit =
+                       (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
+       int result = 0;
+
+       if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
+               if (data->smu_features[GNLD_PPT].supported)
+                       PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
+                                       true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
+                                       "Attempt to enable PPT feature Failed!",
+                                       data->smu_features[GNLD_PPT].supported = false);
+
+               if (data->smu_features[GNLD_TDC].supported)
+                       PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
+                                       true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
+                                       "Attempt to enable PPT feature Failed!",
+                                       data->smu_features[GNLD_TDC].supported = false);
+
+               result = vega12_set_power_limit(hwmgr, default_pwr_limit);
+               PP_ASSERT_WITH_CODE(!result,
+                               "Failed to set Default Power Limit in SMC!",
+                               return result);
+       }
+
+       return result;
+}
+
+int vega12_disable_power_containment(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
+               if (data->smu_features[GNLD_PPT].supported)
+                       PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
+                                       false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
+                                       "Attempt to disable PPT feature Failed!",
+                                       data->smu_features[GNLD_PPT].supported = false);
+
+               if (data->smu_features[GNLD_TDC].supported)
+                       PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
+                                       false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
+                                       "Attempt to disable PPT feature Failed!",
+                                       data->smu_features[GNLD_TDC].supported = false);
+       }
+
+       return 0;
+}
+
+static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
+               uint32_t adjust_percent)
+{
+       return smum_send_msg_to_smc_with_parameter(hwmgr,
+                       PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
+}
+
+int vega12_power_control_set_level(struct pp_hwmgr *hwmgr)
+{
+       int adjust_percent, result = 0;
+
+       if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
+               adjust_percent =
+                               hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
+                               hwmgr->platform_descriptor.TDPAdjustment :
+                               (-1 * hwmgr->platform_descriptor.TDPAdjustment);
+               result = vega12_set_overdrive_target_percentage(hwmgr,
+                               (uint32_t)adjust_percent);
+       }
+       return result;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_powertune.h
new file mode 100644 (file)
index 0000000..78d31a6
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _VEGA12_POWERTUNE_H_
+#define _VEGA12_POWERTUNE_H_
+
+enum vega12_didt_config_reg_type {
+       VEGA12_CONFIGREG_DIDT = 0,
+       VEGA12_CONFIGREG_GCCAC,
+       VEGA12_CONFIGREG_SECAC
+};
+
+/* PowerContainment Features */
+#define POWERCONTAINMENT_FEATURE_DTE             0x00000001
+#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
+#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
+
+struct vega12_didt_config_reg {
+       uint32_t                offset;
+       uint32_t                mask;
+       uint32_t                shift;
+       uint32_t                value;
+};
+
+int vega12_enable_power_containment(struct pp_hwmgr *hwmgr);
+int vega12_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
+int vega12_power_control_set_level(struct pp_hwmgr *hwmgr);
+int vega12_disable_power_containment(struct pp_hwmgr *hwmgr);
+
+int vega12_enable_didt_config(struct pp_hwmgr *hwmgr);
+int vega12_disable_didt_config(struct pp_hwmgr *hwmgr);
+
+#endif  /* _VEGA12_POWERTUNE_H_ */
+
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
new file mode 100644 (file)
index 0000000..e7d7949
--- /dev/null
@@ -0,0 +1,430 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/fb.h>
+
+#include "vega12/smu9_driver_if.h"
+#include "vega12_processpptables.h"
+#include "ppatomfwctrl.h"
+#include "atomfirmware.h"
+#include "pp_debug.h"
+#include "cgs_common.h"
+#include "vega12_pptable.h"
+
+static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
+               enum phm_platform_caps cap)
+{
+       if (enable)
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
+       else
+               phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
+}
+
+static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
+{
+       int index = GetIndexIntoMasterDataTable(powerplayinfo);
+
+       u16 size;
+       u8 frev, crev;
+       const void *table_address = hwmgr->soft_pp_table;
+
+       if (!table_address) {
+               table_address = (ATOM_Vega12_POWERPLAYTABLE *)
+                               cgs_atom_get_data_table(hwmgr->device, index,
+                                               &size, &frev, &crev);
+
+               hwmgr->soft_pp_table = table_address;   /*Cache the result in RAM.*/
+               hwmgr->soft_pp_table_size = size;
+       }
+
+       return table_address;
+}
+
+static int check_powerplay_tables(
+               struct pp_hwmgr *hwmgr,
+               const ATOM_Vega12_POWERPLAYTABLE *powerplay_table)
+{
+       PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
+               ATOM_VEGA12_TABLE_REVISION_VEGA12),
+               "Unsupported PPTable format!", return -1);
+       PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
+               "Invalid PowerPlay Table!", return -1);
+
+       return 0;
+}
+
+static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
+{
+       set_hw_cap(
+                       hwmgr,
+                       0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY),
+                       PHM_PlatformCaps_PowerPlaySupport);
+
+       set_hw_cap(
+                       hwmgr,
+                       0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
+                       PHM_PlatformCaps_BiosPowerSourceControl);
+
+       set_hw_cap(
+                       hwmgr,
+                       0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BACO),
+                       PHM_PlatformCaps_BACO);
+
+       set_hw_cap(
+                       hwmgr,
+                       0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO),
+                        PHM_PlatformCaps_BAMACO);
+
+       return 0;
+}
+
+static int copy_clock_limits_array(
+       struct pp_hwmgr *hwmgr,
+       uint32_t **pptable_info_array,
+       const uint32_t *pptable_array)
+{
+       uint32_t array_size, i;
+       uint32_t *table;
+
+       array_size = sizeof(uint32_t) * ATOM_VEGA12_PPCLOCK_COUNT;
+
+       table = kzalloc(array_size, GFP_KERNEL);
+       if (NULL == table)
+               return -ENOMEM;
+
+       for (i = 0; i < ATOM_VEGA12_PPCLOCK_COUNT; i++)
+               table[i] = pptable_array[i];
+
+       *pptable_info_array = table;
+
+       return 0;
+}
+
+static int copy_overdrive_settings_limits_array(
+               struct pp_hwmgr *hwmgr,
+               uint32_t **pptable_info_array,
+               const uint32_t *pptable_array)
+{
+       uint32_t array_size, i;
+       uint32_t *table;
+
+       array_size = sizeof(uint32_t) * ATOM_VEGA12_ODSETTING_COUNT;
+
+       table = kzalloc(array_size, GFP_KERNEL);
+       if (NULL == table)
+               return -ENOMEM;
+
+       for (i = 0; i < ATOM_VEGA12_ODSETTING_COUNT; i++)
+               table[i] = pptable_array[i];
+
+       *pptable_info_array = table;
+
+       return 0;
+}
+
+static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable)
+{
+       struct pp_atomfwctrl_smc_dpm_parameters smc_dpm_table;
+
+       PP_ASSERT_WITH_CODE(
+               pp_atomfwctrl_get_smc_dpm_information(hwmgr, &smc_dpm_table) == 0,
+               "[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!",
+               return -1);
+
+       ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table.liquid1_i2c_address;
+       ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table.liquid2_i2c_address;
+       ppsmc_pptable->Vr_I2C_address = smc_dpm_table.vr_i2c_address;
+       ppsmc_pptable->Plx_I2C_address = smc_dpm_table.plx_i2c_address;
+
+       ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table.liquid_i2c_linescl;
+       ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table.liquid_i2c_linesda;
+       ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table.vr_i2c_linescl;
+       ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table.vr_i2c_linesda;
+
+       ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table.plx_i2c_linescl;
+       ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table.plx_i2c_linesda;
+       ppsmc_pptable->VrSensorPresent = smc_dpm_table.vrsensorpresent;
+       ppsmc_pptable->LiquidSensorPresent = smc_dpm_table.liquidsensorpresent;
+
+       ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table.maxvoltagestepgfx;
+       ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table.maxvoltagestepsoc;
+
+       ppsmc_pptable->VddGfxVrMapping = smc_dpm_table.vddgfxvrmapping;
+       ppsmc_pptable->VddSocVrMapping = smc_dpm_table.vddsocvrmapping;
+       ppsmc_pptable->VddMem0VrMapping = smc_dpm_table.vddmem0vrmapping;
+       ppsmc_pptable->VddMem1VrMapping = smc_dpm_table.vddmem1vrmapping;
+
+       ppsmc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table.gfxulvphasesheddingmask;
+       ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table.soculvphasesheddingmask;
+
+       ppsmc_pptable->GfxMaxCurrent = smc_dpm_table.gfxmaxcurrent;
+       ppsmc_pptable->GfxOffset = smc_dpm_table.gfxoffset;
+       ppsmc_pptable->Padding_TelemetryGfx = smc_dpm_table.padding_telemetrygfx;
+
+       ppsmc_pptable->SocMaxCurrent = smc_dpm_table.socmaxcurrent;
+       ppsmc_pptable->SocOffset = smc_dpm_table.socoffset;
+       ppsmc_pptable->Padding_TelemetrySoc = smc_dpm_table.padding_telemetrysoc;
+
+       ppsmc_pptable->Mem0MaxCurrent = smc_dpm_table.mem0maxcurrent;
+       ppsmc_pptable->Mem0Offset = smc_dpm_table.mem0offset;
+       ppsmc_pptable->Padding_TelemetryMem0 = smc_dpm_table.padding_telemetrymem0;
+
+       ppsmc_pptable->Mem1MaxCurrent = smc_dpm_table.mem1maxcurrent;
+       ppsmc_pptable->Mem1Offset = smc_dpm_table.mem1offset;
+       ppsmc_pptable->Padding_TelemetryMem1 = smc_dpm_table.padding_telemetrymem1;
+
+       ppsmc_pptable->AcDcGpio = smc_dpm_table.acdcgpio;
+       ppsmc_pptable->AcDcPolarity = smc_dpm_table.acdcpolarity;
+       ppsmc_pptable->VR0HotGpio = smc_dpm_table.vr0hotgpio;
+       ppsmc_pptable->VR0HotPolarity = smc_dpm_table.vr0hotpolarity;
+
+       ppsmc_pptable->VR1HotGpio = smc_dpm_table.vr1hotgpio;
+       ppsmc_pptable->VR1HotPolarity = smc_dpm_table.vr1hotpolarity;
+       ppsmc_pptable->Padding1 = smc_dpm_table.padding1;
+       ppsmc_pptable->Padding2 = smc_dpm_table.padding2;
+
+       ppsmc_pptable->LedPin0 = smc_dpm_table.ledpin0;
+       ppsmc_pptable->LedPin1 = smc_dpm_table.ledpin1;
+       ppsmc_pptable->LedPin2 = smc_dpm_table.ledpin2;
+
+       ppsmc_pptable->GfxclkSpreadEnabled = smc_dpm_table.gfxclkspreadenabled;
+       ppsmc_pptable->GfxclkSpreadPercent = smc_dpm_table.gfxclkspreadpercent;
+       ppsmc_pptable->GfxclkSpreadFreq = smc_dpm_table.gfxclkspreadfreq;
+
+       ppsmc_pptable->UclkSpreadEnabled = 0;
+       ppsmc_pptable->UclkSpreadPercent = smc_dpm_table.uclkspreadpercent;
+       ppsmc_pptable->UclkSpreadFreq = smc_dpm_table.uclkspreadfreq;
+
+       ppsmc_pptable->SocclkSpreadEnabled = 0;
+       ppsmc_pptable->SocclkSpreadPercent = smc_dpm_table.socclkspreadpercent;
+       ppsmc_pptable->SocclkSpreadFreq = smc_dpm_table.socclkspreadfreq;
+
+       return 0;
+}
+
+#define VEGA12_ENGINECLOCK_HARDMAX 198000
+static int init_powerplay_table_information(
+               struct pp_hwmgr *hwmgr,
+               const ATOM_Vega12_POWERPLAYTABLE *powerplay_table)
+{
+       struct phm_ppt_v3_information *pptable_information =
+               (struct phm_ppt_v3_information *)hwmgr->pptable;
+       uint32_t disable_power_control = 0;
+       int result;
+
+       hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType;
+       pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType;
+
+       set_hw_cap(hwmgr,
+               ATOM_VEGA12_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
+               PHM_PlatformCaps_ThermalController);
+
+       phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
+
+       if (powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX] > VEGA12_ENGINECLOCK_HARDMAX)
+               hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX;
+       else
+               hwmgr->platform_descriptor.overdriveLimit.engineClock = powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX];
+       hwmgr->platform_descriptor.overdriveLimit.memoryClock = powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_UCLKFMAX];
+
+       copy_overdrive_settings_limits_array(hwmgr, &pptable_information->od_settings_max, powerplay_table->ODSettingsMax);
+       copy_overdrive_settings_limits_array(hwmgr, &pptable_information->od_settings_min, powerplay_table->ODSettingsMin);
+
+       /* hwmgr->platformDescriptor.minOverdriveVDDC = 0;
+       hwmgr->platformDescriptor.maxOverdriveVDDC = 0;
+       hwmgr->platformDescriptor.overdriveVDDCStep = 0; */
+
+       if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
+               && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0)
+               phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ACOverdriveSupport);
+
+       pptable_information->us_small_power_limit1 = powerplay_table->usSmallPowerLimit1;
+       pptable_information->us_small_power_limit2 = powerplay_table->usSmallPowerLimit2;
+       pptable_information->us_boost_power_limit = powerplay_table->usBoostPowerLimit;
+       pptable_information->us_od_turbo_power_limit = powerplay_table->usODTurboPowerLimit;
+       pptable_information->us_od_powersave_power_limit = powerplay_table->usODPowerSavePowerLimit;
+
+       pptable_information->us_software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
+
+       hwmgr->platform_descriptor.TDPODLimit = (uint16_t)powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_POWERPERCENTAGE];
+
+       disable_power_control = 0;
+       if (!disable_power_control) {
+               /* enable TDP overdrive (PowerControl) feature as well if supported */
+               if (hwmgr->platform_descriptor.TDPODLimit)
+                       phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                               PHM_PlatformCaps_PowerControl);
+       }
+
+       copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_max, powerplay_table->PowerSavingClockMax);
+       copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_min, powerplay_table->PowerSavingClockMin);
+
+       pptable_information->smc_pptable = (PPTable_t *)kmalloc(sizeof(PPTable_t), GFP_KERNEL);
+       if (pptable_information->smc_pptable == NULL)
+               return -ENOMEM;
+
+       memcpy(pptable_information->smc_pptable, &(powerplay_table->smcPPTable), sizeof(PPTable_t));
+
+       result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));
+
+       return result;
+}
+
+int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr)
+{
+       int result = 0;
+       const ATOM_Vega12_POWERPLAYTABLE *powerplay_table;
+
+       hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL);
+       PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
+               "Failed to allocate hwmgr->pptable!", return -ENOMEM);
+
+       powerplay_table = get_powerplay_table(hwmgr);
+       PP_ASSERT_WITH_CODE((powerplay_table != NULL),
+               "Missing PowerPlay Table!", return -1);
+
+       result = check_powerplay_tables(hwmgr, powerplay_table);
+       PP_ASSERT_WITH_CODE((result == 0),
+               "check_powerplay_tables failed", return result);
+
+       result = set_platform_caps(hwmgr,
+                       le32_to_cpu(powerplay_table->ulPlatformCaps));
+       PP_ASSERT_WITH_CODE((result == 0),
+               "set_platform_caps failed", return result);
+
+       result = init_powerplay_table_information(hwmgr, powerplay_table);
+       PP_ASSERT_WITH_CODE((result == 0),
+               "init_powerplay_table_information failed", return result);
+
+       return result;
+}
+
+static int vega12_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
+{
+       struct phm_ppt_v3_information *pp_table_info =
+                       (struct phm_ppt_v3_information *)(hwmgr->pptable);
+
+       kfree(pp_table_info->power_saving_clock_max);
+       pp_table_info->power_saving_clock_max = NULL;
+
+       kfree(pp_table_info->power_saving_clock_min);
+       pp_table_info->power_saving_clock_min = NULL;
+
+       kfree(pp_table_info->od_settings_max);
+       pp_table_info->od_settings_max = NULL;
+
+       kfree(pp_table_info->od_settings_min);
+       pp_table_info->od_settings_min = NULL;
+
+       kfree(pp_table_info->smc_pptable);
+       pp_table_info->smc_pptable = NULL;
+
+       kfree(hwmgr->pptable);
+       hwmgr->pptable = NULL;
+
+       return 0;
+}
+
+const struct pp_table_func vega12_pptable_funcs = {
+       .pptable_init = vega12_pp_tables_initialize,
+       .pptable_fini = vega12_pp_tables_uninitialize,
+};
+
+#if 0
+static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
+               uint16_t classification, uint16_t classification2)
+{
+       uint32_t result = 0;
+
+       if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
+               result |= PP_StateClassificationFlag_Boot;
+
+       if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
+               result |= PP_StateClassificationFlag_Thermal;
+
+       if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
+               result |= PP_StateClassificationFlag_LimitedPowerSource;
+
+       if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
+               result |= PP_StateClassificationFlag_Rest;
+
+       if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
+               result |= PP_StateClassificationFlag_Forced;
+
+       if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
+               result |= PP_StateClassificationFlag_ACPI;
+
+       if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
+               result |= PP_StateClassificationFlag_LimitedPowerSource_2;
+
+       return result;
+}
+
+int vega12_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
+               uint32_t entry_index, struct pp_power_state *power_state,
+               int (*call_back_func)(struct pp_hwmgr *, void *,
+                               struct pp_power_state *, void *, uint32_t))
+{
+       int result = 0;
+       const ATOM_Vega12_State_Array *state_arrays;
+       const ATOM_Vega12_State *state_entry;
+       const ATOM_Vega12_POWERPLAYTABLE *pp_table =
+                       get_powerplay_table(hwmgr);
+
+       PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
+                       return -1;);
+       power_state->classification.bios_index = entry_index;
+
+       if (pp_table->sHeader.format_revision >=
+                       ATOM_Vega12_TABLE_REVISION_VEGA12) {
+               state_arrays = (ATOM_Vega12_State_Array *)
+                               (((unsigned long)pp_table) +
+                               le16_to_cpu(pp_table->usStateArrayOffset));
+
+               PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
+                               "Invalid PowerPlay Table State Array Offset.",
+                               return -1);
+               PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
+                               "Invalid PowerPlay Table State Array.",
+                               return -1);
+               PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
+                               "Invalid PowerPlay Table State Array Entry.",
+                               return -1);
+
+               state_entry = &(state_arrays->states[entry_index]);
+
+               result = call_back_func(hwmgr, (void *)state_entry, power_state,
+                               (void *)pp_table,
+                               make_classification_flags(hwmgr,
+                                       le16_to_cpu(state_entry->usClassification),
+                                       le16_to_cpu(state_entry->usClassification2)));
+       }
+
+       if (!result && (power_state->classification.flags &
+                       PP_StateClassificationFlag_Boot))
+               result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
+
+       return result;
+}
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.h
new file mode 100644 (file)
index 0000000..65652ae
--- /dev/null
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef VEGA12_PROCESSPPTABLES_H
+#define VEGA12_PROCESSPPTABLES_H
+
+#include "hwmgr.h"
+
+enum Vega12_I2CLineID {
+       Vega12_I2CLineID_DDC1 = 0x90,
+       Vega12_I2CLineID_DDC2 = 0x91,
+       Vega12_I2CLineID_DDC3 = 0x92,
+       Vega12_I2CLineID_DDC4 = 0x93,
+       Vega12_I2CLineID_DDC5 = 0x94,
+       Vega12_I2CLineID_DDC6 = 0x95,
+       Vega12_I2CLineID_SCLSDA = 0x96,
+       Vega12_I2CLineID_DDCVGA = 0x97
+};
+
+#define Vega12_I2C_DDC1DATA          0
+#define Vega12_I2C_DDC1CLK           1
+#define Vega12_I2C_DDC2DATA          2
+#define Vega12_I2C_DDC2CLK           3
+#define Vega12_I2C_DDC3DATA          4
+#define Vega12_I2C_DDC3CLK           5
+#define Vega12_I2C_SDA               40
+#define Vega12_I2C_SCL               41
+#define Vega12_I2C_DDC4DATA          65
+#define Vega12_I2C_DDC4CLK           66
+#define Vega12_I2C_DDC5DATA          0x48
+#define Vega12_I2C_DDC5CLK           0x49
+#define Vega12_I2C_DDC6DATA          0x4a
+#define Vega12_I2C_DDC6CLK           0x4b
+#define Vega12_I2C_DDCVGADATA        0x4c
+#define Vega12_I2C_DDCVGACLK         0x4d
+
+extern const struct pp_table_func vega12_pptable_funcs;
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c
new file mode 100644 (file)
index 0000000..df0fa81
--- /dev/null
@@ -0,0 +1,324 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "vega12_thermal.h"
+#include "vega12_hwmgr.h"
+#include "vega12_smumgr.h"
+#include "vega12_ppsmc.h"
+#include "vega12_inc.h"
+#include "pp_soc15.h"
+#include "pp_debug.h"
+
+static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
+{
+       PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
+                               PPSMC_MSG_GetCurrentRpm),
+                       "Attempt to get current RPM from SMC Failed!",
+                       return -1);
+       PP_ASSERT_WITH_CODE(!vega12_read_arg_from_smc(hwmgr,
+                       current_rpm),
+                       "Attempt to read current RPM from SMC Failed!",
+                       return -1);
+       return 0;
+}
+
+int vega12_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
+               struct phm_fan_speed_info *fan_speed_info)
+{
+       memset(fan_speed_info, 0, sizeof(*fan_speed_info));
+       fan_speed_info->supports_percent_read = false;
+       fan_speed_info->supports_percent_write = false;
+       fan_speed_info->supports_rpm_read = true;
+       fan_speed_info->supports_rpm_write = true;
+
+       return 0;
+}
+
+int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
+{
+       *speed = 0;
+
+       return vega12_get_current_rpm(hwmgr, speed);
+}
+
+/**
+ * @fn vega12_enable_fan_control_feature
+ * @brief Enables the SMC Fan Control Feature.
+ *
+ * @param    hwmgr - the address of the powerplay hardware manager.
+ * @return   0 on success. -1 otherwise.
+ */
+static int vega12_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
+{
+#if 0
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (data->smu_features[GNLD_FAN_CONTROL].supported) {
+               PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(
+                               hwmgr, true,
+                               data->smu_features[GNLD_FAN_CONTROL].
+                               smu_feature_bitmap),
+                               "Attempt to Enable FAN CONTROL feature Failed!",
+                               return -1);
+               data->smu_features[GNLD_FAN_CONTROL].enabled = true;
+       }
+#endif
+       return 0;
+}
+
+static int vega12_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
+{
+#if 0
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (data->smu_features[GNLD_FAN_CONTROL].supported) {
+               PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(
+                               hwmgr, false,
+                               data->smu_features[GNLD_FAN_CONTROL].
+                               smu_feature_bitmap),
+                               "Attempt to Enable FAN CONTROL feature Failed!",
+                               return -1);
+               data->smu_features[GNLD_FAN_CONTROL].enabled = false;
+       }
+#endif
+       return 0;
+}
+
+int vega12_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (data->smu_features[GNLD_FAN_CONTROL].supported)
+               PP_ASSERT_WITH_CODE(
+                               !vega12_enable_fan_control_feature(hwmgr),
+                               "Attempt to Enable SMC FAN CONTROL Feature Failed!",
+                               return -1);
+
+       return 0;
+}
+
+
+int vega12_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+
+       if (data->smu_features[GNLD_FAN_CONTROL].supported)
+               PP_ASSERT_WITH_CODE(!vega12_disable_fan_control_feature(hwmgr),
+                               "Attempt to Disable SMC FAN CONTROL Feature Failed!",
+                               return -1);
+
+       return 0;
+}
+
+/**
+* Reset Fan Speed to default.
+* @param    hwmgr  the address of the powerplay hardware manager.
+* @exception Always succeeds.
+*/
+int vega12_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
+{
+       return vega12_fan_ctrl_start_smc_fan_control(hwmgr);
+}
+
+/**
+* Reads the remote temperature from the SIslands thermal controller.
+*
+* @param    hwmgr The address of the hardware manager.
+*/
+int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr)
+{
+       int temp = 0;
+       uint32_t reg;
+
+       reg = soc15_get_register_offset(THM_HWID, 0,
+                       mmCG_MULT_THERMAL_STATUS_BASE_IDX,  mmCG_MULT_THERMAL_STATUS);
+
+       temp = cgs_read_register(hwmgr->device, reg);
+
+       temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
+                       CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
+
+       temp = temp & 0x1ff;
+
+       temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+       return temp;
+}
+
+/**
+* Set the requested temperature range for high and low alert signals
+*
+* @param    hwmgr The address of the hardware manager.
+* @param    range Temperature range to be programmed for
+*           high and low alert signals
+* @exception PP_Result_BadInput if the input data is not valid.
+*/
+static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
+               struct PP_TemperatureRange *range)
+{
+       int low = VEGA12_THERMAL_MINIMUM_ALERT_TEMP *
+                       PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+       int high = VEGA12_THERMAL_MAXIMUM_ALERT_TEMP *
+                       PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+       uint32_t val, reg;
+
+       if (low < range->min)
+               low = range->min;
+       if (high > range->max)
+               high = range->max;
+
+       if (low > high)
+               return -EINVAL;
+
+       reg = soc15_get_register_offset(THM_HWID, 0,
+                       mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);
+
+       val = cgs_read_register(hwmgr->device, reg);
+
+       val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
+       val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
+       val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+       val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+       val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
+
+       cgs_write_register(hwmgr->device, reg, val);
+
+       return 0;
+}
+
+/**
+* Enable thermal alerts on the RV770 thermal controller.
+*
+* @param    hwmgr The address of the hardware manager.
+*/
+static int vega12_thermal_enable_alert(struct pp_hwmgr *hwmgr)
+{
+       uint32_t val = 0;
+       uint32_t reg;
+
+       val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
+       val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
+       val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
+
+       reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
+       cgs_write_register(hwmgr->device, reg, val);
+
+       return 0;
+}
+
+/**
+* Disable thermal alerts on the RV770 thermal controller.
+* @param    hwmgr The address of the hardware manager.
+*/
+int vega12_thermal_disable_alert(struct pp_hwmgr *hwmgr)
+{
+       uint32_t reg;
+
+       reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
+       cgs_write_register(hwmgr->device, reg, 0);
+
+       return 0;
+}
+
+/**
+* Uninitialize the thermal controller.
+* Currently just disables alerts.
+* @param    hwmgr The address of the hardware manager.
+*/
+int vega12_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
+{
+       int result = vega12_thermal_disable_alert(hwmgr);
+
+       return result;
+}
+
+/**
+* Set up the fan table to control the fan using the SMC.
+* @param    hwmgr  the address of the powerplay hardware manager.
+* @param    pInput the pointer to input data
+* @param    pOutput the pointer to output data
+* @param    pStorage the pointer to temporary storage
+* @param    Result the last failure code
+* @return   result from set temperature range routine
+*/
+int vega12_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
+{
+       int ret;
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       PPTable_t *table = &(data->smc_state_table.pp_table);
+
+       ret = smum_send_msg_to_smc_with_parameter(hwmgr,
+                               PPSMC_MSG_SetFanTemperatureTarget,
+                               (uint32_t)table->FanTargetTemperature);
+
+       return ret;
+}
+
+/**
+* Start the fan control on the SMC.
+* @param    hwmgr  the address of the powerplay hardware manager.
+* @param    pInput the pointer to input data
+* @param    pOutput the pointer to output data
+* @param    pStorage the pointer to temporary storage
+* @param    Result the last failure code
+* @return   result from set temperature range routine
+*/
+int vega12_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
+{
+       /* If the fantable setup has failed we could have disabled
+        * PHM_PlatformCaps_MicrocodeFanControl even after
+        * this function was included in the table.
+        * Make sure that we still think controlling the fan is OK.
+        */
+       if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
+               vega12_fan_ctrl_start_smc_fan_control(hwmgr);
+
+       return 0;
+}
+
+
+int vega12_start_thermal_controller(struct pp_hwmgr *hwmgr,
+                               struct PP_TemperatureRange *range)
+{
+       int ret = 0;
+
+       if (range == NULL)
+               return -EINVAL;
+
+       ret = vega12_thermal_set_temperature_range(hwmgr, range);
+       if (ret)
+               return -EINVAL;
+
+       vega12_thermal_enable_alert(hwmgr);
+       /* We should restrict performance levels to low before we halt the SMC.
+        * On the other hand we are still in boot state when we do this
+        * so it would be pointless.
+        * If this assumption changes we have to revisit this table.
+        */
+       ret = vega12_thermal_setup_fan_table(hwmgr);
+       if (ret)
+               return -EINVAL;
+
+       vega12_thermal_start_smc_fan_control(hwmgr);
+
+       return 0;
+};
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h
new file mode 100644 (file)
index 0000000..0d8ed03
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef VEGA12_THERMAL_H
+#define VEGA12_THERMAL_H
+
+#include "hwmgr.h"
+
+struct vega12_temperature {
+       uint16_t edge_temp;
+       uint16_t hot_spot_temp;
+       uint16_t hbm_temp;
+       uint16_t vr_soc_temp;
+       uint16_t vr_mem_temp;
+       uint16_t liquid1_temp;
+       uint16_t liquid2_temp;
+       uint16_t plx_temp;
+};
+
+#define VEGA12_THERMAL_HIGH_ALERT_MASK         0x1
+#define VEGA12_THERMAL_LOW_ALERT_MASK          0x2
+
+#define VEGA12_THERMAL_MINIMUM_TEMP_READING    -256
+#define VEGA12_THERMAL_MAXIMUM_TEMP_READING    255
+
+#define VEGA12_THERMAL_MINIMUM_ALERT_TEMP      0
+#define VEGA12_THERMAL_MAXIMUM_ALERT_TEMP      255
+
+#define FDO_PWM_MODE_STATIC  1
+#define FDO_PWM_MODE_STATIC_RPM 5
+
+extern int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr);
+extern int vega12_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
+extern int vega12_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
+               struct phm_fan_speed_info *fan_speed_info);
+extern int vega12_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
+extern int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr,
+               uint32_t *speed);
+extern int vega12_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
+extern int vega12_thermal_disable_alert(struct pp_hwmgr *hwmgr);
+extern int vega12_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
+extern int vega12_start_thermal_controller(struct pp_hwmgr *hwmgr,
+                               struct PP_TemperatureRange *range);
+
+#endif
+
index b366a5bd2d8156dad84555c47419f2666d7e895d..19f2e43480cbb3319daff6517f0662581cd1272d 100644 (file)
@@ -232,6 +232,20 @@ enum phm_platform_caps {
        PHM_PlatformCaps_UVDClientMCTuning,
        PHM_PlatformCaps_ODNinACSupport,
        PHM_PlatformCaps_ODNinDCSupport,
+       PHM_PlatformCaps_UMDPState,
+       PHM_PlatformCaps_AutoWattmanSupport,
+       PHM_PlatformCaps_AutoWattmanEnable_CCCState,
+       PHM_PlatformCaps_FreeSyncActive,
+       PHM_PlatformCaps_EnableShadowPstate,
+       PHM_PlatformCaps_customThermalManagement,
+       PHM_PlatformCaps_staticFanControl,
+       PHM_PlatformCaps_Virtual_System,
+       PHM_PlatformCaps_LowestUclkReservedForUlv,
+       PHM_PlatformCaps_EnableBoostState,
+       PHM_PlatformCaps_AVFSSupport,
+       PHM_PlatformCaps_ThermalPolicyDelay,
+       PHM_PlatformCaps_CustomFanControlSupport,
+       PHM_PlatformCaps_BAMACO,
        PHM_PlatformCaps_Max
 };
 
index 85b46ad68546ee6df4d96eac22f9e0776544a767..4b3b05747a3f8fcd85109e75452bc0310c80d276 100644 (file)
@@ -585,6 +585,27 @@ struct phm_ppt_v2_information {
        uint8_t  uc_dcef_dpm_voltage_mode;
 };
 
+struct phm_ppt_v3_information
+{
+       uint8_t uc_thermal_controller_type;
+
+       uint16_t us_small_power_limit1;
+       uint16_t us_small_power_limit2;
+       uint16_t us_boost_power_limit;
+
+       uint16_t us_od_turbo_power_limit;
+       uint16_t us_od_powersave_power_limit;
+       uint16_t us_software_shutdown_temp;
+
+       uint32_t *power_saving_clock_max;
+       uint32_t *power_saving_clock_min;
+
+       uint32_t *od_settings_max;
+       uint32_t *od_settings_min;
+
+       void *smc_pptable;
+};
+
 struct phm_dynamic_state_info {
        struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
        struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;