arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets

On several QUSB2 Targets, the hs_phy_irq mentioned is actually
qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
to qusb2_phy for such targets.

In actuality, the hs_phy_irq is also present in these targets, but
kept in for debug purposes in hw test environments. This is not
triggered by default and its functionality is mutually exclusive
to that of qusb2_phy interrupt.

Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
Add missing ss_phy_irq on some targets which allows for remote
wakeup to work on a Super Speed link.

Also modify order of interrupts in accordance to bindings update.
Since driver looks up for interrupts by name and not by index, it
is safe to modify order of these interrupts in the DT.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 5e1277fea7250b4132039efb18f1cfaafdc5257e..e84adf14be24dcf0d8fd21953edb68e92a886b4c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -418,6 +418,12 @@
                                          <&gcc GCC_USB1_MOCK_UTMI_CLK>;
                        assigned-clock-rates = <133330000>,
                                               <24000000>;
+
+                       interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy";
+
                        resets = <&gcc GCC_USB1_BCR>;
                        status = "disabled";
 
@@ -630,6 +636,13 @@
                                               <133330000>,
                                               <24000000>;
 
+                       interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "ss_phy_irq";
+
                        resets = <&gcc GCC_USB0_BCR>;
                        status = "disabled";
 

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index cf295bed32998087cee60bd0ce61d0cf587d2c0a..cb42278515fe0f9787ffb8ebf7dac56634f7bb97 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -627,6 +627,13 @@
                                                <133330000>,
                                                <19200000>;
 
+                       interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "ss_phy_irq";
+
                        power-domains = <&gcc USB0_GDSC>;
 
                        resets = <&gcc GCC_USB0_BCR>;
@@ -669,6 +676,13 @@
                                                <133330000>,
                                                <19200000>;
 
+                       interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "ss_phy_irq";
+
                        power-domains = <&gcc USB1_GDSC>;
 
                        resets = <&gcc GCC_USB1_BCR>;

diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index ad2f8cf9c966c568cdc517b1ccd7939ded23e57c..8bd1499b5c8fa4fa68623759bfdbae012535f137 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -1160,9 +1160,12 @@
                        #size-cells = <1>;
                        ranges;
 
-                       interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                       interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "hs_phy_irq", "ss_phy_irq";
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "ss_phy_irq";
 
                        clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
                                 <&gcc GCC_USB30_MASTER_CLK>,

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 8d41ed261adfbfc99e15c07755f54d8f4cf5cc80..600720d3a8f5f0a953a0c6349a052954d7d059b3 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -3408,8 +3408,12 @@
                        #size-cells = <1>;
                        ranges;
 
-                       interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "hs_phy_irq";
+                       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "hs_phy_irq";
 
                        clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
                                <&gcc GCC_USB20_MASTER_CLK>,

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 2793cc22d381af990a80018b96e16da4400d0fd1..348eee866451638f1a0a5dbe5155ef17c0167f7c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -2132,9 +2132,12 @@
                                          <&gcc GCC_USB30_MASTER_CLK>;
                        assigned-clock-rates = <19200000>, <120000000>;
 
-                       interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+                       interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "hs_phy_irq", "ss_phy_irq";
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "ss_phy_irq";
 
                        power-domains = <&gcc USB_30_GDSC>;
 

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 513fe5e76b688ed0ace12b3804169fdb7e2c8841..940901474804b030de759635c1f24765be94170b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1281,9 +1281,14 @@
                                          <&gcc GCC_USB30_MASTER_CLK>;
                        assigned-clock-rates = <19200000>, <120000000>;
 
-                       interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+                       interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "hs_phy_irq", "ss_phy_irq";
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "hs_phy_irq",
+                                         "ss_phy_irq";
 
                        power-domains = <&gcc USB_30_GDSC>;
                        qcom,select-utmi-as-pipe-clk;
@@ -1463,8 +1468,12 @@
                                          <&gcc GCC_USB20_MASTER_CLK>;
                        assigned-clock-rates = <19200000>, <60000000>;
 
-                       interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "hs_phy_irq";
+                       interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "hs_phy_irq";
 
                        qcom,select-utmi-as-pipe-clk;
 

diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 160e098f10757e5f4e9c68e82ecc45f1ce27aa14..cf8e72f06f8e5fd64aed9a77d846cb0cb7898abc 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -1586,9 +1586,14 @@
                                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
                        assigned-clock-rates = <19200000>, <66666667>;
 
-                       interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                       interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "hs_phy_irq", "ss_phy_irq";
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "hs_phy_irq",
+                                         "ss_phy_irq";
 
                        resets = <&gcc GCC_USB30_PRIM_BCR>;
                        power-domains = <&gcc GCC_USB30_PRIM_GDSC>;

diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 1dd3a4056e26f3888dcc95e300f44f289f99d8bb..00a2e0980163cef36afa6da5acea5fe776207938 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -1185,9 +1185,14 @@
                                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
                        assigned-clock-rates = <19200000>, <66666667>;
 
-                       interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                       interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "hs_phy_irq", "ss_phy_irq";
+                       interrupt-names = "pwr_event",
+                                         "qusb2_phy",
+                                         "hs_phy_irq",
+                                         "ss_phy_irq";
 
                        power-domains = <&gcc USB30_PRIM_GDSC>;
                        qcom,select-utmi-as-pipe-clk;