drm/imagination: Remove firmware enable_reg

After a previous commit ("drm/imagination: Mask GPU IRQs in threaded
handler"), this register is now only used to enable firmware interrupts at
start-of-day. This is, however, unnecessary since they are enabled by
default.

In addition, the soon-to-be-added RISC-V firmware processors do not have
an equivalent register.

Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-8-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>

diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/imagination/pvr_device.c
index a47dd1dd82432f1d66ff90aca26b7b264f4068df..1e488a30c7840466574c7fc3648ab93edfb46354 100644 (file)
--- a/drivers/gpu/drm/imagination/pvr_device.c
+++ b/drivers/gpu/drm/imagination/pvr_device.c
@@ -311,7 +311,6 @@ pvr_device_irq_init(struct pvr_device *pvr_dev)
 
        /* Clear any pending events before requesting the IRQ line. */
        pvr_fw_irq_clear(pvr_dev);
-       pvr_fw_irq_enable(pvr_dev);
 
        if (pvr_dev->has_safety_events)
                pvr_device_safety_irq_clear(pvr_dev);

diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h
index b7966bd574a924862b7877c175fa2b5d757d89db..29bae4bc244a243a6a95bcf838d924060cc043e2 100644 (file)
--- a/drivers/gpu/drm/imagination/pvr_fw.h
+++ b/drivers/gpu/drm/imagination/pvr_fw.h
@@ -188,9 +188,6 @@ struct pvr_fw_defs {
         * processor backend in pvr_fw_funcs::init().
         */
        struct {
-               /** @enable_reg: FW interrupt enable register. */
-               u32 enable_reg;
-
                /** @status_reg: FW interrupt status register. */
                u32 status_reg;
 
@@ -202,7 +199,7 @@ struct pvr_fw_defs {
                 */
                u32 clear_reg;
 
-               /** @event_mask: Bitmask of events to listen for. */
+               /** @event_mask: Bitmask of events to listen for in the status_reg. */
                u32 event_mask;
 
                /** @clear_mask: Value to write to the clear_reg in order to clear FW IRQs. */
@@ -412,12 +409,6 @@ struct pvr_fw_device {
 #define pvr_fw_irq_clear(pvr_dev) \
        pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_mask)
 
-#define pvr_fw_irq_enable(pvr_dev) \
-       pvr_fw_irq_write_reg(pvr_dev, enable, (pvr_dev)->fw_dev.defs->irq.event_mask)
-
-#define pvr_fw_irq_disable(pvr_dev) \
-       pvr_fw_irq_write_reg(pvr_dev, enable, 0)
-
 extern const struct pvr_fw_defs pvr_fw_defs_meta;
 extern const struct pvr_fw_defs pvr_fw_defs_mips;
 

diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c
index c7cfdd60116d5fd1e9fa93945653c938fafba07e..77596a2a6c4e9c9e2b3af6b9b2aea3ad49062550 100644 (file)
--- a/drivers/gpu/drm/imagination/pvr_fw_meta.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c
@@ -547,7 +547,6 @@ const struct pvr_fw_defs pvr_fw_defs_meta = {
        .wrapper_init = pvr_meta_wrapper_init,
        .has_fixed_data_addr = pvr_meta_has_fixed_data_addr,
        .irq = {
-               .enable_reg = ROGUE_CR_META_SP_MSLVIRQENABLE,
                .status_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS,
                .clear_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS,
                .event_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN,

diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/imagination/pvr_fw_mips.c
index ee0735b745a9ff5c99637c2cb312998679f47fd3..c73902bcf8e46ee58174a503cc7f235f2d45d180 100644 (file)
--- a/drivers/gpu/drm/imagination/pvr_fw_mips.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c
@@ -241,7 +241,6 @@ const struct pvr_fw_defs pvr_fw_defs_mips = {
        .wrapper_init = pvr_mips_wrapper_init,
        .has_fixed_data_addr = pvr_mips_has_fixed_data_addr,
        .irq = {
-               .enable_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE,
                .status_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS,
                .clear_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR,
                .event_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN,