drm/i915: Add GuC TLB Invalidation device info flags
authorJonathan Cavitt <jonathan.cavitt@intel.com>
Tue, 17 Oct 2023 18:08:00 +0000 (11:08 -0700)
committerAndi Shyti <andi.shyti@linux.intel.com>
Wed, 18 Oct 2023 04:01:07 +0000 (06:01 +0200)
Add device info flags for if GuC TLB Invalidation is enabled.

Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231017180806.3054290-2-jonathan.cavitt@intel.com
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_device_info.h

index 11bc7e5f40122648253933e801aca1683a12e3fe..3737307bb12ad5823b2ebcf13d54e8e23c1c7d85 100644 (file)
@@ -856,6 +856,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_GUC_DEPRIVILEGE(i915) \
        (INTEL_INFO(i915)->has_guc_deprivilege)
 
+#define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)
+
 #define HAS_3D_PIPELINE(i915)  (INTEL_INFO(i915)->has_3d_pipeline)
 
 #define HAS_ONE_EU_PER_FUSE_BIT(i915)  (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
index 2ca54417d19b5109d92c7ad2356e405c8c16482d..f7d7d67ff6cfc6d735cba8bfbd3ada80992d2cb3 100644 (file)
@@ -154,6 +154,7 @@ enum intel_ppgtt_type {
        func(has_heci_pxp); \
        func(has_heci_gscfi); \
        func(has_guc_deprivilege); \
+       func(has_guc_tlb_invalidation); \
        func(has_l3_ccs_read); \
        func(has_l3_dpf); \
        func(has_llc); \