drm/i915/color: move palette registers to intel_color_regs.h

For some reason the paletter registers were missed when adding
intel_color_regs.h. Finish the job. Adjust some comments while at it.

v2: Fix comments (Ville)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1322f577b113b8fc1a6c2ef35340fc3c599b4bcb.1714128645.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h
index ec8732401cd87e908c07e844ba2943362af3c704..02033c882d7f8aac09b381ea81f6a97d88c74900 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_color_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
@@ -8,7 +8,35 @@
 
 #include "intel_display_reg_defs.h"
 
-/* legacy palette */
+/* GMCH palette */
+#define _PALETTE_A             0xa000
+#define _PALETTE_B             0xa800
+#define _CHV_PALETTE_C         0xc000
+/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
+#define   PALETTE_RED_MASK             REG_GENMASK(23, 16)
+#define   PALETTE_GREEN_MASK           REG_GENMASK(15, 8)
+#define   PALETTE_BLUE_MASK            REG_GENMASK(7, 0)
+/* pre-i965 10bit interpolated mode ldw */
+#define   PALETTE_10BIT_RED_LDW_MASK   REG_GENMASK(23, 16)
+#define   PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
+#define   PALETTE_10BIT_BLUE_LDW_MASK  REG_GENMASK(7, 0)
+/* pre-i965 10bit interpolated mode udw */
+#define   PALETTE_10BIT_RED_EXP_MASK   REG_GENMASK(23, 22)
+#define   PALETTE_10BIT_RED_MANT_MASK  REG_GENMASK(21, 18)
+#define   PALETTE_10BIT_RED_UDW_MASK   REG_GENMASK(17, 16)
+#define   PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
+#define   PALETTE_10BIT_GREEN_MANT_MASK        REG_GENMASK(13, 10)
+#define   PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
+#define   PALETTE_10BIT_BLUE_EXP_MASK  REG_GENMASK(7, 6)
+#define   PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
+#define   PALETTE_10BIT_BLUE_UDW_MASK  REG_GENMASK(1, 0)
+#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +                   \
+                              _PICK_EVEN_2RANGES(pipe, 2,                      \
+                                                 _PALETTE_A, _PALETTE_B,       \
+                                                 _CHV_PALETTE_C, _CHV_PALETTE_C) + \
+                                                 (i) * 4)
+
+/* ilk+ palette */
 #define _LGC_PALETTE_A           0x4a000
 #define _LGC_PALETTE_B           0x4a800
 /* see PALETTE_* for the bits */

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4913b9a371c09fba3f2855b7c44b2aa89cbfc8b9..c5ea2ed653b9292f57f6e92049dd7172f3bad9c0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1440,36 +1440,6 @@
 
 #define GMBUSFREQ_VLV          _MMIO(VLV_DISPLAY_BASE + 0x6510)
 
-/*
- * Palette regs
- */
-#define _PALETTE_A             0xa000
-#define _PALETTE_B             0xa800
-#define _CHV_PALETTE_C         0xc000
-/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
-#define   PALETTE_RED_MASK             REG_GENMASK(23, 16)
-#define   PALETTE_GREEN_MASK           REG_GENMASK(15, 8)
-#define   PALETTE_BLUE_MASK            REG_GENMASK(7, 0)
-/* pre-i965 10bit interpolated mode ldw */
-#define   PALETTE_10BIT_RED_LDW_MASK   REG_GENMASK(23, 16)
-#define   PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
-#define   PALETTE_10BIT_BLUE_LDW_MASK  REG_GENMASK(7, 0)
-/* pre-i965 10bit interpolated mode udw */
-#define   PALETTE_10BIT_RED_EXP_MASK   REG_GENMASK(23, 22)
-#define   PALETTE_10BIT_RED_MANT_MASK  REG_GENMASK(21, 18)
-#define   PALETTE_10BIT_RED_UDW_MASK   REG_GENMASK(17, 16)
-#define   PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
-#define   PALETTE_10BIT_GREEN_MANT_MASK        REG_GENMASK(13, 10)
-#define   PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
-#define   PALETTE_10BIT_BLUE_EXP_MASK  REG_GENMASK(7, 6)
-#define   PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
-#define   PALETTE_10BIT_BLUE_UDW_MASK  REG_GENMASK(1, 0)
-#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +                   \
-                              _PICK_EVEN_2RANGES(pipe, 2,                      \
-                                                 _PALETTE_A, _PALETTE_B,       \
-                                                 _CHV_PALETTE_C, _CHV_PALETTE_C) + \
-                                                 (i) * 4)
-
 #define PEG_BAND_GAP_DATA      _MMIO(0x14d68)
 
 #define BXT_RP_STATE_CAP        _MMIO(0x138170)