arm: dts: calxeda: Basic DT file fixes

The .dts files for the Calxeda machines are quite old, so carry some
sloppy mistakes that the DT schema checker will complain about.

Fix those issues, they should not have any effect on functionality.

Link: https://lore.kernel.org/r/20200228135106.220620-2-andre.przywara@arm.com
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
index 5651ae6dc969692651627e5a52f9898ef3c0cde1..8e0489607704524d94ffe76252f4e20e3f8a734d 100644 (file)
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -13,7 +13,6 @@
        compatible = "calxeda,ecx-2000";
        #address-cells = <2>;
        #size-cells = <2>;
-       clock-ranges;
 
        cpus {
                #address-cells = <1>;
@@ -83,8 +82,7 @@
                intc: interrupt-controller@fff11000 {
                        compatible = "arm,cortex-a15-gic";
                        #interrupt-cells = <3>;
-                       #size-cells = <0>;
-                       #address-cells = <1>;
+                       #address-cells = <0>;
                        interrupt-controller;
                        interrupts = <1 9 0xf04>;
                        reg = <0xfff11000 0x1000>,

diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index f4e4dca6f7e7072c05f11eaa138945e261ce96fd..9e34d1bd7994656540d3d30e517251f050c5dcd6 100644 (file)
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -13,7 +13,6 @@
        compatible = "calxeda,highbank";
        #address-cells = <1>;
        #size-cells = <1>;
-       clock-ranges;
 
        cpus {
                #address-cells = <1>;
@@ -96,7 +95,7 @@
                };
        };
 
-       memory {
+       memory@0 {
                name = "memory";
                device_type = "memory";
                reg = <0x00000000 0xff900000>;
@@ -128,14 +127,12 @@
                intc: interrupt-controller@fff11000 {
                        compatible = "arm,cortex-a9-gic";
                        #interrupt-cells = <3>;
-                       #size-cells = <0>;
-                       #address-cells = <1>;
                        interrupt-controller;
                        reg = <0xfff11000 0x1000>,
                              <0xfff10100 0x100>;
                };
 
-               L2: l2-cache {
+               L2: cache-controller {
                        compatible = "arm,pl310-cache";
                        reg = <0xfff12000 0x1000>;
                        interrupts = <0 70 4>;