arm64: dts: imx8: switch to two cell scu clock binding

switch to two cell scu clock binding

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 9301166ea629d7416d9e71dc3f9aa91d6638f830..30f2089cfdc42b2b5b60ed32c8125d7659083527 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -113,7 +113,7 @@ adma_subsys: bus@59000000 {
        uart0_lpcg: clock-controller@5a460000 {
                reg = <0x5a460000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_ADMA_UART0_CLK>,
+               clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
                         <&dma_ipg_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
                clock-output-names = "uart0_lpcg_baud_clk",
@@ -124,7 +124,7 @@ adma_subsys: bus@59000000 {
        uart1_lpcg: clock-controller@5a470000 {
                reg = <0x5a470000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_ADMA_UART1_CLK>,
+               clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
                         <&dma_ipg_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
                clock-output-names = "uart1_lpcg_baud_clk",
@@ -135,7 +135,7 @@ adma_subsys: bus@59000000 {
        uart2_lpcg: clock-controller@5a480000 {
                reg = <0x5a480000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_ADMA_UART2_CLK>,
+               clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
                         <&dma_ipg_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
                clock-output-names = "uart2_lpcg_baud_clk",
@@ -146,7 +146,7 @@ adma_subsys: bus@59000000 {
        uart3_lpcg: clock-controller@5a490000 {
                reg = <0x5a490000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_ADMA_UART3_CLK>,
+               clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
                         <&dma_ipg_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
                clock-output-names = "uart3_lpcg_baud_clk",
@@ -159,7 +159,7 @@ adma_subsys: bus@59000000 {
                interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
                clock-names = "per";
-               assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
+               assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                power-domains = <&pd IMX_SC_R_I2C_0>;
                status = "disabled";
@@ -170,7 +170,7 @@ adma_subsys: bus@59000000 {
                interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
                clock-names = "per";
-               assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
+               assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                power-domains = <&pd IMX_SC_R_I2C_1>;
                status = "disabled";
@@ -181,7 +181,7 @@ adma_subsys: bus@59000000 {
                interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
                clock-names = "per";
-               assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
+               assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                power-domains = <&pd IMX_SC_R_I2C_2>;
                status = "disabled";
@@ -192,7 +192,7 @@ adma_subsys: bus@59000000 {
                interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
                clock-names = "per";
-               assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
+               assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                power-domains = <&pd IMX_SC_R_I2C_3>;
                status = "disabled";
@@ -201,7 +201,7 @@ adma_subsys: bus@59000000 {
        i2c0_lpcg: clock-controller@5ac00000 {
                reg = <0x5ac00000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_ADMA_I2C0_CLK>,
+               clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
                         <&dma_ipg_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
                clock-output-names = "i2c0_lpcg_clk",
@@ -212,7 +212,7 @@ adma_subsys: bus@59000000 {
        i2c1_lpcg: clock-controller@5ac10000 {
                reg = <0x5ac10000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_ADMA_I2C1_CLK>,
+               clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
                         <&dma_ipg_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
                clock-output-names = "i2c1_lpcg_clk",
@@ -223,7 +223,7 @@ adma_subsys: bus@59000000 {
        i2c2_lpcg: clock-controller@5ac20000 {
                reg = <0x5ac20000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_ADMA_I2C2_CLK>,
+               clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
                         <&dma_ipg_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
                clock-output-names = "i2c2_lpcg_clk",
@@ -234,7 +234,7 @@ adma_subsys: bus@59000000 {
        i2c3_lpcg: clock-controller@5ac30000 {
                reg = <0x5ac30000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_ADMA_I2C3_CLK>,
+               clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
                         <&dma_ipg_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
                clock-output-names = "i2c3_lpcg_clk",

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index c5ab23aff45275cb9a2adc1de942ee27f33bc867..e2fe3bc2bceaf05bba36cfeeb520c2d9d7270606 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -112,7 +112,7 @@ conn_subsys: bus@5b000000 {
        sdhc0_lpcg: clock-controller@5b200000 {
                reg = <0x5b200000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_CONN_SDHC0_CLK>,
+               clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
                         <&conn_ipg_clk>, <&conn_axi_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
                                <IMX_LPCG_CLK_5>;
@@ -125,7 +125,7 @@ conn_subsys: bus@5b000000 {
        sdhc1_lpcg: clock-controller@5b210000 {
                reg = <0x5b210000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_CONN_SDHC1_CLK>,
+               clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
                         <&conn_ipg_clk>, <&conn_axi_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
                                <IMX_LPCG_CLK_5>;
@@ -138,7 +138,7 @@ conn_subsys: bus@5b000000 {
        sdhc2_lpcg: clock-controller@5b220000 {
                reg = <0x5b220000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_CONN_SDHC2_CLK>,
+               clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
                         <&conn_ipg_clk>, <&conn_axi_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
                                <IMX_LPCG_CLK_5>;
@@ -151,8 +151,8 @@ conn_subsys: bus@5b000000 {
        enet0_lpcg: clock-controller@5b230000 {
                reg = <0x5b230000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>,
-                        <&clk IMX_CONN_ENET0_ROOT_CLK>,
+               clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
                         <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
                                <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
@@ -168,8 +168,8 @@ conn_subsys: bus@5b000000 {
        enet1_lpcg: clock-controller@5b240000 {
                reg = <0x5b240000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>,
-                        <&clk IMX_CONN_ENET1_ROOT_CLK>,
+               clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
                         <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
                                <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index babe6c3e2c760878aff1bca4d1aeb331a2a29b6e..813dbac71d101ee9c47236a534adc44e3b4377e2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -157,9 +157,11 @@ lsio_subsys: bus@5d000000 {
        pwm0_lpcg: clock-controller@5d400000 {
                reg = <0x5d400000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_LSIO_PWM0_CLK>, <&clk IMX_LSIO_PWM0_CLK>,
-                        <&clk IMX_LSIO_PWM0_CLK>, <&lsio_bus_clk>,
-                        <&clk IMX_LSIO_PWM0_CLK>;
+               clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+                        <&lsio_bus_clk>,
+                        <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
                                <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
                                <IMX_LPCG_CLK_6>;
@@ -174,9 +176,11 @@ lsio_subsys: bus@5d000000 {
        pwm1_lpcg: clock-controller@5d410000 {
                reg = <0x5d410000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_LSIO_PWM1_CLK>, <&clk IMX_LSIO_PWM1_CLK>,
-                        <&clk IMX_LSIO_PWM1_CLK>, <&lsio_bus_clk>,
-                        <&clk IMX_LSIO_PWM1_CLK>;
+               clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+                        <&lsio_bus_clk>,
+                        <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
                                <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
                                <IMX_LPCG_CLK_6>;
@@ -191,9 +195,11 @@ lsio_subsys: bus@5d000000 {
        pwm2_lpcg: clock-controller@5d420000 {
                reg = <0x5d420000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_LSIO_PWM2_CLK>, <&clk IMX_LSIO_PWM2_CLK>,
-                        <&clk IMX_LSIO_PWM2_CLK>, <&lsio_bus_clk>,
-                        <&clk IMX_LSIO_PWM2_CLK>;
+               clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+                        <&lsio_bus_clk>,
+                        <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
                                <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
                                <IMX_LPCG_CLK_6>;
@@ -208,9 +214,11 @@ lsio_subsys: bus@5d000000 {
        pwm3_lpcg: clock-controller@5d430000 {
                reg = <0x5d430000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_LSIO_PWM3_CLK>, <&clk IMX_LSIO_PWM3_CLK>,
-                        <&clk IMX_LSIO_PWM3_CLK>, <&lsio_bus_clk>,
-                        <&clk IMX_LSIO_PWM3_CLK>;
+               clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+                        <&lsio_bus_clk>,
+                        <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
                                <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
                                <IMX_LPCG_CLK_6>;
@@ -225,9 +233,11 @@ lsio_subsys: bus@5d000000 {
        pwm4_lpcg: clock-controller@5d440000 {
                reg = <0x5d440000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_LSIO_PWM4_CLK>, <&clk IMX_LSIO_PWM4_CLK>,
-                        <&clk IMX_LSIO_PWM4_CLK>, <&lsio_bus_clk>,
-                        <&clk IMX_LSIO_PWM4_CLK>;
+               clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+                        <&lsio_bus_clk>,
+                        <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
                                <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
                                <IMX_LPCG_CLK_6>;
@@ -242,9 +252,11 @@ lsio_subsys: bus@5d000000 {
        pwm5_lpcg: clock-controller@5d450000 {
                reg = <0x5d450000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_LSIO_PWM5_CLK>, <&clk IMX_LSIO_PWM5_CLK>,
-                        <&clk IMX_LSIO_PWM5_CLK>, <&lsio_bus_clk>,
-                        <&clk IMX_LSIO_PWM5_CLK>;
+               clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+                        <&lsio_bus_clk>,
+                        <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
                                <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
                                <IMX_LPCG_CLK_6>;
@@ -259,9 +271,11 @@ lsio_subsys: bus@5d000000 {
        pwm6_lpcg: clock-controller@5d460000 {
                reg = <0x5d460000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_LSIO_PWM6_CLK>, <&clk IMX_LSIO_PWM6_CLK>,
-                        <&clk IMX_LSIO_PWM6_CLK>, <&lsio_bus_clk>,
-                        <&clk IMX_LSIO_PWM6_CLK>;
+               clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+                        <&lsio_bus_clk>,
+                        <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
                                <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
                                <IMX_LPCG_CLK_6>;
@@ -276,9 +290,11 @@ lsio_subsys: bus@5d000000 {
        pwm7_lpcg: clock-controller@5d470000 {
                reg = <0x5d470000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&clk IMX_LSIO_PWM7_CLK>, <&clk IMX_LSIO_PWM7_CLK>,
-                        <&clk IMX_LSIO_PWM7_CLK>, <&lsio_bus_clk>,
-                        <&clk IMX_LSIO_PWM7_CLK>;
+               clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+                        <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+                        <&lsio_bus_clk>,
+                        <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
                                <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
                                <IMX_LPCG_CLK_6>;

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
index a3f8cf1959747c8a7efa730f34e86db44a6777e4..b5352706e3f0ac51580c479283f85a5705d71c9c 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
@@ -133,7 +133,7 @@
 &usdhc1 {
        #address-cells = <1>;
        #size-cells = <0>;
-       assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
+       assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
        assigned-clock-rates = <200000000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc1>;
@@ -151,7 +151,7 @@
 
 /* SD */
 &usdhc2 {
-       assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
+       assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
        assigned-clock-rates = <200000000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc2>;

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 46437d3c7a043b0006230e2bcb01016730c00b2a..c40bbb313b780d6a6639ea6c7b4a698d7baa42e4 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -173,7 +173,7 @@
 };
 
 &usdhc1 {
-       assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
+       assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
        assigned-clock-rates = <200000000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc1>;
@@ -185,7 +185,7 @@
 };
 
 &usdhc2 {
-       assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
+       assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
        assigned-clock-rates = <200000000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc2>;

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index cd7a482dc3ff1e262098a9464e874de7cef5220a..095d3f69a9b7d09f46fd98b1a548ab9f4f2b3692 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -58,7 +58,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        next-level-cache = <&A35_L2>;
-                       clocks = <&clk IMX_A35_CLK>;
+                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
                        operating-points-v2 = <&a35_opp_table>;
                        #cooling-cells = <2>;
                };
@@ -69,7 +69,7 @@
                        reg = <0x0 0x1>;
                        enable-method = "psci";
                        next-level-cache = <&A35_L2>;
-                       clocks = <&clk IMX_A35_CLK>;
+                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
                        operating-points-v2 = <&a35_opp_table>;
                        #cooling-cells = <2>;
                };
@@ -80,7 +80,7 @@
                        reg = <0x0 0x2>;
                        enable-method = "psci";
                        next-level-cache = <&A35_L2>;
-                       clocks = <&clk IMX_A35_CLK>;
+                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
                        operating-points-v2 = <&a35_opp_table>;
                        #cooling-cells = <2>;
                };
@@ -91,7 +91,7 @@
                        reg = <0x0 0x3>;
                        enable-method = "psci";
                        next-level-cache = <&A35_L2>;
-                       clocks = <&clk IMX_A35_CLK>;
+                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
                        operating-points-v2 = <&a35_opp_table>;
                        #cooling-cells = <2>;
                };
@@ -165,7 +165,7 @@
 
                clk: clock-controller {
                        compatible = "fsl,imx8qxp-clk";
-                       #clock-cells = <1>;
+                       #clock-cells = <2>;
                        clocks = <&xtal32k &xtal24m>;
                        clock-names = "xtal_32KHz", "xtal_24Mhz";
                };