Merge tag 'riscv-mw2-6.16-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel...

riscv patches for 6.16-rc1, part 2

* Performance improvements
  - Add support for vdso getrandom
  - Implement raid6 calculations using vectors
  - Introduce svinval tlb invalidation

* Cleanup
  - A bunch of deduplication of the macros we use for manipulating instructions

* Misc
  - Introduce a kunit test for kprobes
  - Add support for mseal as riscv fits the requirements (thanks to Lorenzo for making sure of that :))

[Palmer: There was a rebase between part 1 and part 2, so I've had to do
some more git surgery here... at least two rounds of surgery...]

* alex-pr-2: (866 commits)
  RISC-V: vDSO: Wire up getrandom() vDSO implementation
  riscv: enable mseal sysmap for RV64
  raid6: Add RISC-V SIMD syndrome and recovery calculations
  riscv: mm: Add support for Svinval extension
  riscv: Add kprobes KUnit test
  riscv: kprobes: Remove duplication of RV_EXTRACT_ITYPE_IMM
  riscv: kprobes: Remove duplication of RV_EXTRACT_UTYPE_IMM
  riscv: kprobes: Remove duplication of RV_EXTRACT_RD_REG
  riscv: kprobes: Remove duplication of RVC_EXTRACT_BTYPE_IMM
  riscv: kprobes: Remove duplication of RVC_EXTRACT_C2_RS1_REG
  riscv: kproves: Remove duplication of RVC_EXTRACT_JTYPE_IMM
  riscv: kprobes: Remove duplication of RV_EXTRACT_BTYPE_IMM
  riscv: kprobes: Remove duplication of RV_EXTRACT_RS1_REG
  riscv: kprobes: Remove duplication of RV_EXTRACT_JTYPE_IMM
  riscv: kprobes: Move branch_funct3 to insn.h
  riscv: kprobes: Move branch_rs2_idx to insn.h
  Linux 6.15-rc6
  Input: xpad - fix xpad_device sorting
  Input: xpad - add support for several more controllers
  Input: xpad - fix Share button on Xbox One controllers
  ...

diff --cc .mailmap
Simple merge

diff --cc MAINTAINERS
Simple merge

diff --cc arch/riscv/Kconfig
Simple merge

diff --cc arch/riscv/include/asm/cacheflush.h
index effa02c2e682faa9f56b5d466588dcc4e04c5dee,b59ffeb668d6a50149457079a967a4b6c25fa557..6086b38d54279d4227c04fe0628f598f9941832f
--- 1/arch/riscv/include/asm/cacheflush.h
--- 2/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@@ -78,9 -73,18 +73,19 @@@ void flush_icache_mm(struct mm_struct *
  
  #endif /* CONFIG_SMP */
  
+ /*
+  * RISC-V doesn't have an instruction to flush parts of the instruction cache,
+  * so instead we just flush the whole thing.
+  */
+ #define flush_icache_range flush_icache_range
+ static inline void flush_icache_range(unsigned long start, unsigned long end)
+ {
+       flush_icache_all();
+ }
+ 
  extern unsigned int riscv_cbom_block_size;
  extern unsigned int riscv_cboz_block_size;
 +extern unsigned int riscv_cbop_block_size;
  void riscv_init_cbo_blocksizes(void);
  
  #ifdef CONFIG_RISCV_DMA_NONCOHERENT

diff --cc arch/riscv/kernel/Makefile
Simple merge

diff --cc arch/riscv/kernel/traps_misaligned.c
Simple merge

diff --cc arch/riscv/kernel/vdso/Makefile
Simple merge

diff --cc arch/riscv/mm/tlbflush.c
Simple merge

diff --cc kernel/trace/ftrace.c
Simple merge