arm64: dts: mediatek: mt8188: Add DP-INTF nodes

Add the primary and secondary dp-intf nodes.
These DP-INTF hardware IPs are the sink of the vdosys0 and vdosys1
display pipelines for the internal and external displays, respectively.

Individual board device tree should enable the nodes and connect input
and output ports as needed.

Signed-off-by: Fei Shao <fshao@chromium.org>
Link: https://lore.kernel.org/r/20241014111053.2294519-9-fshao@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 5e602416062fe89b66233b1e115cd094864ab52e..0935f2ccb2b010dabf3c503b99dc6016a29312c1 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -24,6 +24,8 @@
        #size-cells = <2>;
 
        aliases {
+               dp-intf0 = &dp_intf0;
+               dp-intf1 = &dp_intf1;
                ethdr0 = &ethdr0;
                gce0 = &gce0;
                gce1 = &gce1;
@@ -2480,6 +2482,18 @@
                        status = "disabled";
                };
 
+               dp_intf0: dp-intf@1c015000 {
+                       compatible = "mediatek,mt8188-dp-intf";
+                       reg = <0 0x1c015000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+                                <&vdosys0 CLK_VDO0_DP_INTF0>,
+                                <&apmixedsys CLK_APMIXED_TVDPLL1>;
+                       clock-names = "pixel", "engine", "pll";
+                       interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       status = "disabled";
+               };
+
                mutex0: mutex@1c016000 {
                        compatible = "mediatek,mt8188-disp-mutex";
                        reg = <0 0x1c016000 0 0x1000>;
@@ -2745,6 +2759,18 @@
                        mediatek,merge-fifo-en;
                };
 
+               dp_intf1: dp-intf@1c113000 {
+                       compatible = "mediatek,mt8188-dp-intf";
+                       reg = <0 0x1c113000 0 0x1000>;
+                       clocks = <&vdosys1 CLK_VDO1_DPINTF>,
+                                <&vdosys1 CLK_VDO1_DP_INTF0_MMCK>,
+                                <&apmixedsys CLK_APMIXED_TVDPLL2>;
+                       clock-names = "pixel", "engine", "pll";
+                       interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+                       status = "disabled";
+               };
+
                ethdr0: ethdr@1c114000 {
                        compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr";
                        reg = <0 0x1c114000 0 0x1000>,