drm/i915/mtl: do not enable render power-gating on MTL

Multiple CI tests fails with forcewake ack timeouts if render
power gating is enabled.
BSpec 52698 states it should be 0 for MTL, but apparently
this info is outdated. Anyway since the patch makes MTL pass basic
tests added FIXME tag informing this is temporary workaround.

v2: added FIXME tag

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230517-mtl_disable_render_pg-v2-1-0b51180a43f0@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 908a3d0f2343f4066d8b835b0c23e5870048e518..58bb1c55294c939848b4f8dc4d79059c0245350e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -117,8 +117,14 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
                        GEN6_RC_CTL_RC6_ENABLE |
                        GEN6_RC_CTL_EI_MODE(1);
 
-       /* Wa_16011777198 - Render powergating must remain disabled */
-       if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
+       /*
+        * Wa_16011777198 and BSpec 52698 - Render powergating must be off.
+        * FIXME BSpec is outdated, disabling powergating for MTL is just
+        * temporary wa and should be removed after fixing real cause
+        * of forcewake timeouts.
+        */
+       if (IS_METEORLAKE(gt->i915) ||
+           IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
            IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
                pg_enable =
                        GEN9_MEDIA_PG_ENABLE |