for (i = 0; i < ARRAY_SIZE(mca->mca_caches); i++) {
mca_cache = &mca->mca_caches[i];
- mutex_init(&mca_cache->lock);
+ spin_lock_init(&mca_cache->lock);
amdgpu_mca_bank_set_init(&mca_cache->mca_set);
}
for (i = 0; i < ARRAY_SIZE(mca->mca_caches); i++) {
mca_cache = &mca->mca_caches[i];
amdgpu_mca_bank_set_release(&mca_cache->mca_set);
- mutex_destroy(&mca_cache->lock);
}
}
struct mca_bank_cache *mca_cache = &adev->mca.mca_caches[type];
int ret;
- mutex_lock(&mca_cache->lock);
+ spin_lock(&mca_cache->lock);
ret = amdgpu_mca_bank_set_merge(&mca_cache->mca_set, new);
- mutex_unlock(&mca_cache->lock);
+ spin_unlock(&mca_cache->lock);
return ret;
}
}
/* dispatch mca set again if mca cache has valid data */
- mutex_lock(&mca_cache->lock);
+ spin_lock(&mca_cache->lock);
if (mca_cache->mca_set.nr_entries)
ret = amdgpu_mca_dispatch_mca_set(adev, blk, type, &mca_cache->mca_set, err_data);
- mutex_unlock(&mca_cache->lock);
+ spin_unlock(&mca_cache->lock);
out_mca_release:
amdgpu_mca_bank_set_release(&mca_set);