arm64: dts: ti: k3-j721e-main: Add #clock-cells property to serdes DT node

Add #clock-cells property to serdes DT node since the serdes is also now
modeled as a clock provider and include the input clocks "pll0_refclk"
and "pll1_refclk" which are parents to the clocks modeled by serdes.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603143427.28735-3-kishon@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index cc3428f99b9a382c9d8371febfa4bf216dbfc4da..2ce17cafffe21422718dabc0089a3386a5444e29 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -402,10 +402,13 @@
                        reg = <0x5000000 0x10000>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       #clock-cells = <1>;
                        resets = <&serdes_wiz0 0>;
                        reset-names = "sierra_reset";
-                       clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
-                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+                       clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
+                                <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
+                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+                                     "pll0_refclk", "pll1_refclk";
                };
        };
 
@@ -459,10 +462,13 @@
                        reg = <0x5010000 0x10000>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       #clock-cells = <1>;
                        resets = <&serdes_wiz1 0>;
                        reset-names = "sierra_reset";
-                       clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
-                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+                       clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
+                                <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
+                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+                                     "pll0_refclk", "pll1_refclk";
                };
        };
 
@@ -516,10 +522,13 @@
                        reg = <0x5020000 0x10000>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       #clock-cells = <1>;
                        resets = <&serdes_wiz2 0>;
                        reset-names = "sierra_reset";
-                       clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
-                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+                       clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
+                                <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
+                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+                                     "pll0_refclk", "pll1_refclk";
                };
        };
 
@@ -573,10 +582,13 @@
                        reg = <0x5030000 0x10000>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       #clock-cells = <1>;
                        resets = <&serdes_wiz3 0>;
                        reset-names = "sierra_reset";
-                       clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
-                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+                       clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
+                                <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
+                       clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+                                     "pll0_refclk", "pll1_refclk";
                };
        };