[Why]
A cleaner solution, only done once on boot.
[How]
Remove previous workaround and configure an extra
vmid one time on boot
Reviewed-by: Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
}
return false;
}
-
-static void apply_riommu_invalidation_wa(struct dc *dc)
-{
- struct dce_hwseq *hws = dc->hwseq;
-
- if (!hws->wa.early_riommu_invalidation)
- return;
-
- REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, 0);
-}
-
-void dcn31_init_pipes(struct dc *dc, struct dc_state *context)
-{
- dcn10_init_pipes(dc, context);
- apply_riommu_invalidation_wa(dc);
-
-}
};
static const struct hwseq_private_funcs dcn31_private_funcs = {
- .init_pipes = dcn31_init_pipes,
+ .init_pipes = dcn10_init_pipes,
.update_plane_addr = dcn20_update_plane_addr,
.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
.update_mpcc = dcn20_update_mpcc,
hws->regs = &hwseq_reg;
hws->shifts = &hwseq_shift;
hws->masks = &hwseq_mask;
- hws->wa.early_riommu_invalidation = true;
}
return hws;
}
bool DEGVIDCN10_254;
bool DEGVIDCN21;
bool disallow_self_refresh_during_multi_plane_transition;
- bool early_riommu_invalidation;
};
struct hwseq_wa_state {