staging: rtl8192e: Join constants Rtl819XRadioB_.. with ..RadioB_..
authorPhilipp Hortmann <philipp.g.hortmann@gmail.com>
Tue, 14 Mar 2023 18:44:07 +0000 (19:44 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 16 Mar 2023 08:37:19 +0000 (09:37 +0100)
Join constants Rtl819XRadioB_Array with Rtl8192PciERadioB_Array to
RTL8192E_RADIO_B_ARR to improve readability. Fix spaces around '+' to
improve coding style.

Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/59af481400d5f7633bcaf7fcd95b7e5f0093fd3f.1678814935.git.philipp.g.hortmann@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c
drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h
drivers/staging/rtl8192e/rtl8192e/table.c
drivers/staging/rtl8192e/rtl8192e/table.h

index 49fdaacb788a135f880608a091aa5277684286e1..5b9a1b78c35e941c38ca9dc2061a774b59e398e4 100644 (file)
@@ -555,13 +555,13 @@ u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath)
                break;
        case RF90_PATH_B:
                for (i = 0; i < RTL8192E_RADIO_B_ARR_LEN; i += 2) {
-                       if (Rtl819XRadioB_Array[i] == 0xfe) {
+                       if (RTL8192E_RADIO_B_ARR[i] == 0xfe) {
                                msleep(100);
                                continue;
                        }
-                       rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i],
+                       rtl92e_set_rf_reg(dev, eRFPath, RTL8192E_RADIO_B_ARR[i],
                                          bMask12Bits,
-                                         Rtl819XRadioB_Array[i+1]);
+                                         RTL8192E_RADIO_B_ARR[i + 1]);
 
                }
                break;
index 74c7850e514c0d0c149726264fdd39fa3fc05067..ee91d687de9bfa237246b734f177154056313210 100644 (file)
@@ -9,7 +9,6 @@
 
 #define MAX_DOZE_WAITING_TIMES_9x 64
 
-#define Rtl819XRadioB_Array                    Rtl8192PciERadioB_Array
 #define Rtl819XAGCTAB_Array                    Rtl8192PciEAGCTAB_Array
 #define Rtl819XPHY_REG_1T2RArray               Rtl8192PciEPHY_REG_1T2RArray
 
index 4f36a480f6f29e2f616de030265ed084ee354724..eeea01681e7da7f872015f2b32b784aefad812bc 100644 (file)
@@ -283,7 +283,7 @@ u32 RTL8192E_RADIO_A_ARR[RTL8192E_RADIO_A_ARR_LEN] = {
        0x007, 0x00000700,
 };
 
-u32 Rtl8192PciERadioB_Array[RTL8192E_RADIO_B_ARR_LEN] = {
+u32 RTL8192E_RADIO_B_ARR[RTL8192E_RADIO_B_ARR_LEN] = {
        0x019, 0x00000003,
        0x000, 0x000000bf,
        0x001, 0x000006e0,
index 60917c95842b7b7d217a4b9af277f149bc9a98c5..3023440db58bb0190312f7e2fecc124e0f0863aa 100644 (file)
@@ -16,7 +16,7 @@ extern u32 Rtl8192PciEPHY_REG_1T2RArray[RTL8192E_PHY_REG_1T2R_ARR_LEN];
 #define RTL8192E_RADIO_A_ARR_LEN 246
 extern u32 RTL8192E_RADIO_A_ARR[RTL8192E_RADIO_A_ARR_LEN];
 #define RTL8192E_RADIO_B_ARR_LEN 78
-extern u32 Rtl8192PciERadioB_Array[RTL8192E_RADIO_B_ARR_LEN];
+extern u32 RTL8192E_RADIO_B_ARR[RTL8192E_RADIO_B_ARR_LEN];
 #define RTL8192E_MACPHY_ARR_LEN 18
 extern u32 RTL8192E_MACPHY_ARR[RTL8192E_MACPHY_ARR_LEN];
 #define RTL8192E_MACPHY_ARR_PG_LEN 30