arm64: dts: qcom: ipq6018: switch PCIe QMP PHY to new style of bindings

Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-9-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 47b8b1d6730ac664f43509b491a838d255fcf60f..3c8a2f4e26a3966bc81c65685ed1f962e8a01d2d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -278,33 +278,25 @@
 
                pcie_phy: phy@84000 {
                        compatible = "qcom,ipq6018-qmp-pcie-phy";
-                       reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
+                       reg = <0x0 0x00084000 0x0 0x1000>;
                        status = "disabled";
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
 
                        clocks = <&gcc GCC_PCIE0_AUX_CLK>,
-                               <&gcc GCC_PCIE0_AHB_CLK>;
-                       clock-names = "aux", "cfg_ahb";
+                               <&gcc GCC_PCIE0_AHB_CLK>,
+                               <&gcc GCC_PCIE0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "pipe";
+
+                       clock-output-names = "gcc_pcie0_pipe_clk_src";
+                       #clock-cells = <0>;
+
+                       #phy-cells = <0>;
 
                        resets = <&gcc GCC_PCIE0_PHY_BCR>,
                                <&gcc GCC_PCIE0PHY_PHY_BCR>;
                        reset-names = "phy",
                                      "common";
-
-                       pcie_phy0: phy@84200 {
-                               reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
-                                     <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
-                                     <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
-                                     <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
-                               #phy-cells = <0>;
-
-                               clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-                               clock-names = "pipe0";
-                               clock-output-names = "gcc_pcie0_pipe_clk_src";
-                               #clock-cells = <0>;
-                       };
                };
 
                mdio: mdio@90000 {
@@ -756,7 +748,7 @@
                        #address-cells = <3>;
                        #size-cells = <2>;
 
-                       phys = <&pcie_phy0>;
+                       phys = <&pcie_phy>;
                        phy-names = "pciephy";
 
                        ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,