iio: adc: ad7768-1: Add reset gpio

Implement asynchronous hardware reset GPIO.

Reviewed-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>
Co-developed-by: Jonathan Santos <Jonathan.Santos@analog.com>
Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
Link: https://patch.msgid.link/25a413babeddf29583f1c26abf4234dfd606a595.1744325346.git.Jonathan.Santos@analog.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c
index 017d24d0bcd8525b9d22bf64e16c33c1eb08178c..34712d3756e2283d3e539fadf1d8dc193f474708 100644 (file)
--- a/drivers/iio/adc/ad7768-1.c
+++ b/drivers/iio/adc/ad7768-1.c
@@ -163,6 +163,7 @@ struct ad7768_state {
        struct completion completion;
        struct iio_trigger *trig;
        struct gpio_desc *gpio_sync_in;
+       struct gpio_desc *gpio_reset;
        const char *labels[ARRAY_SIZE(ad7768_channels)];
        /*
         * DMA (thus cache coherency maintenance) may require the
@@ -487,19 +488,30 @@ static int ad7768_setup(struct ad7768_state *st)
 {
        int ret;
 
-       /*
-        * Two writes to the SPI_RESET[1:0] bits are required to initiate
-        * a software reset. The bits must first be set to 11, and then
-        * to 10. When the sequence is detected, the reset occurs.
-        * See the datasheet, page 70.
-        */
-       ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x3);
-       if (ret)
-               return ret;
+       st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
+                                                GPIOD_OUT_HIGH);
+       if (IS_ERR(st->gpio_reset))
+               return PTR_ERR(st->gpio_reset);
 
-       ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x2);
-       if (ret)
-               return ret;
+       if (st->gpio_reset) {
+               fsleep(10);
+               gpiod_set_value_cansleep(st->gpio_reset, 0);
+               fsleep(200);
+       } else {
+               /*
+                * Two writes to the SPI_RESET[1:0] bits are required to initiate
+                * a software reset. The bits must first be set to 11, and then
+                * to 10. When the sequence is detected, the reset occurs.
+                * See the datasheet, page 70.
+                */
+               ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x3);
+               if (ret)
+                       return ret;
+
+               ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x2);
+               if (ret)
+                       return ret;
+       }
 
        st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in",
                                          GPIOD_OUT_LOW);