PCI: Use min_align, not unrelated add_align, for size0

Commit 566f1dd52816 ("PCI: Relax bridge window tail sizing rules")
relaxed bridge window tail alignment rule for the non-optional part
(size0, no add_size/add_align). The required alignment given for
pbus_upstream_space_available(), however, was add_align which relates
only to size1 alignment.

As pbus_upstream_space_available() only selects between normal and relaxed
tail alignment of the bridge window, the different alignment only makes
relaxed tail alignment to be used more often than what was intended, which
should be harmless because relaxed tail alignment itself should work in all
cases.

For consistency, change pbus_upstream_space_available() call to use
min_align which is the alignment that is going to be used for the bridge
window in the case where size0 sized allocation is attempted.

Link: https://lore.kernel.org/r/20241216175632.4175-3-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Xiaochun Lee <lixc17@lenovo.com>

diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 3a1fcaad142a4079c02f3dce9f99d6c81f10d199..326badd4192a020deb576d4042279b7e4a17ded2 100644 (file)
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -1145,7 +1145,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
 
        if (bus->self && size0 &&
            !pbus_upstream_space_available(bus, mask | IORESOURCE_PREFETCH, type,
-                                          size0, add_align)) {
+                                          size0, min_align)) {
                min_align = 1ULL << (max_order + __ffs(SZ_1M));
                min_align = max(min_align, win_align);
                size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), win_align);