drm/bridge: imx: add bridge wrapper driver for i.MX8MP DWC HDMI

Add a simple wrapper driver for the DWC HDMI bridge driver that
implements the few bits that are necessary to abstract the i.MX8MP
SoC integration.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20240203165307.7806-11-aford173@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240203165307.7806-11-aford173@gmail.com

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index a4d13331e320109e0f2251cd53d76db07edb877a..5965e8027529a19cb36c58d6c0335ce0db613b21 100644 (file)
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -3,6 +3,17 @@ if ARCH_MXC || COMPILE_TEST
 config DRM_IMX_LDB_HELPER
        tristate
 
+config DRM_IMX8MP_DW_HDMI_BRIDGE
+       tristate "Freescale i.MX8MP HDMI-TX bridge support"
+       depends on OF
+       depends on COMMON_CLK
+       select DRM_DW_HDMI
+       select DRM_IMX8MP_HDMI_PVI
+       select PHY_FSL_SAMSUNG_HDMI_PHY
+       help
+         Choose this to enable support for the internal HDMI encoder found
+         on the i.MX8MP SoC.
+
 config DRM_IMX8MP_HDMI_PVI
        tristate "Freescale i.MX8MP HDMI PVI bridge support"
        depends on OF

diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index e2c2106509facb9870e33af8e90b0019e7807989..edb0a7b71b30a361898e5c08f995299c3210634b 100644 (file)
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_DRM_IMX_LDB_HELPER) += imx-ldb-helper.o
+obj-$(CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE) += imx8mp-hdmi-tx.o
 obj-$(CONFIG_DRM_IMX8MP_HDMI_PVI) += imx8mp-hdmi-pvi.o
 obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o
 obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o

diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
new file mode 100644 (file)
index 0000000..89fc432
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <linux/clk.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <drm/bridge/dw_hdmi.h>
+#include <drm/drm_modes.h>
+
+struct imx8mp_hdmi {
+       struct dw_hdmi_plat_data plat_data;
+       struct dw_hdmi *dw_hdmi;
+       struct clk *pixclk;
+};
+
+static enum drm_mode_status
+imx8mp_hdmi_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
+                      const struct drm_display_info *info,
+                      const struct drm_display_mode *mode)
+{
+       struct imx8mp_hdmi *hdmi = (struct imx8mp_hdmi *)data;
+
+       if (mode->clock < 13500)
+               return MODE_CLOCK_LOW;
+
+       if (mode->clock > 297000)
+               return MODE_CLOCK_HIGH;
+
+       if (clk_round_rate(hdmi->pixclk, mode->clock * 1000) !=
+           mode->clock * 1000)
+               return MODE_CLOCK_RANGE;
+
+       /* We don't support double-clocked and Interlaced modes */
+       if ((mode->flags & DRM_MODE_FLAG_DBLCLK) ||
+           (mode->flags & DRM_MODE_FLAG_INTERLACE))
+               return MODE_BAD;
+
+       return MODE_OK;
+}
+
+static int imx8mp_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data,
+                               const struct drm_display_info *display,
+                               const struct drm_display_mode *mode)
+{
+       return 0;
+}
+
+static void imx8mp_hdmi_phy_disable(struct dw_hdmi *dw_hdmi, void *data)
+{
+}
+
+static void im8mp_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
+{
+       /*
+        * Just release PHY core from reset, all other power management is done
+        * by the PHY driver.
+        */
+       dw_hdmi_phy_gen1_reset(hdmi);
+
+       dw_hdmi_phy_setup_hpd(hdmi, data);
+}
+
+static const struct dw_hdmi_phy_ops imx8mp_hdmi_phy_ops = {
+       .init           = imx8mp_hdmi_phy_init,
+       .disable        = imx8mp_hdmi_phy_disable,
+       .setup_hpd      = im8mp_hdmi_phy_setup_hpd,
+       .read_hpd       = dw_hdmi_phy_read_hpd,
+       .update_hpd     = dw_hdmi_phy_update_hpd,
+};
+
+static int imx8mp_dw_hdmi_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       struct dw_hdmi_plat_data *plat_data;
+       struct imx8mp_hdmi *hdmi;
+
+       hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
+       if (!hdmi)
+               return -ENOMEM;
+
+       plat_data = &hdmi->plat_data;
+
+       hdmi->pixclk = devm_clk_get(dev, "pix");
+       if (IS_ERR(hdmi->pixclk))
+               return dev_err_probe(dev, PTR_ERR(hdmi->pixclk),
+                                    "Unable to get pixel clock\n");
+
+       plat_data->mode_valid = imx8mp_hdmi_mode_valid;
+       plat_data->phy_ops = &imx8mp_hdmi_phy_ops;
+       plat_data->phy_name = "SAMSUNG HDMI TX PHY";
+       plat_data->priv_data = hdmi;
+       plat_data->phy_force_vendor = true;
+
+       hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data);
+       if (IS_ERR(hdmi->dw_hdmi))
+               return PTR_ERR(hdmi->dw_hdmi);
+
+       platform_set_drvdata(pdev, hdmi);
+
+       return 0;
+}
+
+static int imx8mp_dw_hdmi_remove(struct platform_device *pdev)
+{
+       struct imx8mp_hdmi *hdmi = platform_get_drvdata(pdev);
+
+       dw_hdmi_remove(hdmi->dw_hdmi);
+
+       return 0;
+}
+
+static int __maybe_unused imx8mp_dw_hdmi_pm_suspend(struct device *dev)
+{
+       return 0;
+}
+
+static int __maybe_unused imx8mp_dw_hdmi_pm_resume(struct device *dev)
+{
+       struct imx8mp_hdmi *hdmi = dev_get_drvdata(dev);
+
+       dw_hdmi_resume(hdmi->dw_hdmi);
+
+       return 0;
+}
+
+static const struct dev_pm_ops imx8mp_dw_hdmi_pm_ops = {
+       SET_SYSTEM_SLEEP_PM_OPS(imx8mp_dw_hdmi_pm_suspend,
+                               imx8mp_dw_hdmi_pm_resume)
+};
+
+static const struct of_device_id imx8mp_dw_hdmi_of_table[] = {
+       { .compatible = "fsl,imx8mp-hdmi-tx" },
+       { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8mp_dw_hdmi_of_table);
+
+static struct platform_driver imx8mp_dw_hdmi_platform_driver = {
+       .probe          = imx8mp_dw_hdmi_probe,
+       .remove         = imx8mp_dw_hdmi_remove,
+       .driver         = {
+               .name   = "imx8mp-dw-hdmi-tx",
+               .of_match_table = imx8mp_dw_hdmi_of_table,
+               .pm = &imx8mp_dw_hdmi_pm_ops,
+       },
+};
+
+module_platform_driver(imx8mp_dw_hdmi_platform_driver);
+
+MODULE_DESCRIPTION("i.MX8MP HDMI encoder driver");
+MODULE_LICENSE("GPL");